Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology

AN-YEU(ANDY) WUWu, An-YeuAn-YeuWuChan, Tsun-ShanTsun-ShanChanAN-YEU(ANDY) WU2018-09-102018-09-101998http://www.scopus.com/inward/record.url?eid=2-s2.0-0031624396&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/341360Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technologyconference paper