Lebeck, Alvin R.Alvin R.LebeckRaymond, David R.David R.RaymondCHIA-LIN YANGThottethodi, MithunaMithunaThottethodi2020-05-042020-05-04199903029743https://scholars.lib.ntu.edu.tw/handle/123456789/487806https://www.scopus.com/inward/record.uri?eid=2-s2.0-84878641871&doi=10.1007%2f3-540-48311-x_177&partnerID=40&md5=07d0b53044a9d22c2aedf012b09718cbAs the importance of cache performance increases, allowing software to assist in cache management decisions becomes an attractive alternative. This paper focuses primarily on a mechanism for software to convey information to the memory hierarchy. We introduce a single instruction - called TAG - that can annotate subsequent memory references with a number of bits, thus avoiding major modifications to the instruction set. Simulation results show that annotating all memory reference instructions in the SPEC95 benchmarks increases execution time between 0% and 2% for both statically and dynamically scheduleded processors. We show that exposing cache management mechanisms to software can decrease the execution time of three media benchmarks (epic, pegwit, ijpeg) between 11% and 17% speedups on a 4-issue dynamically scheduled processor. © Springer-Verlag Berlin Heidelberg 1999.Parallel processing systems; Cache management; Cache performance; Dynamically-scheduled processor; Instruction set; Memory hierarchy; Memory reference instructions; Memory references; Cache memoryconference paper10.1007/3-540-48311-X_1772-s2.0-84878641871https://doi.org/10.1007/3-540-48311-X_177