A rule-based compactor for VLSI/CAD mask layout

Inst. of Electr. Eng., National Taiwan Univ.Hsiao, Pei-YungPei-YungHsiaoChen, Yung SyauYung SyauChenFeng, Wu-ShiungWu-ShiungFengParng, T.M.T.M.ParngHsu, C.C.C.C.Hsu2007-04-192018-07-062007-04-192018-07-061988-10http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032124application/pdf422224 bytesapplication/pdfen-USA rule-based compactor for VLSI/CAD mask layoutjournal article10.1109/CMPSAC.1988.17146http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032124/1/00017146.pdf