A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

Graduate Inst. of Electron. Eng., National Taiwan Univ.AN-YEU(ANDY) WUWey, I.-C.I.-C.WeyChang, L.-H.L.-H.ChangChen, Y.-G.Y.-G.ChenChang, S.-H.S.-H.ChangAN-YEU(ANDY) WU2018-09-102018-09-102005http://www.scopus.com/inward/record.url?eid=2-s2.0-67649088653&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/316745application/pdf528659 bytesapplication/pdf[SDGs]SDG7A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applicationsconference paper10.1109/ISCAS.2005.1464778