Chen T.-SHsieh H.-YLIANG-HUNG LU2022-04-252022-04-252021https://www.scopus.com/inward/record.uri?eid=2-s2.0-85118189503&doi=10.1109%2fRFIT52905.2021.9565285&partnerID=40&md5=c6d7768066bcc4ec7800395a4aa4759bhttps://scholars.lib.ntu.edu.tw/handle/123456789/607247This paper implements a phase-locked loop based on ring-oscillator operating at 2.4GHz in a TSMC 180 nm CMOS process. It combines a sub-sampling and time-based integrator technology. First, the sub-sampling feature is used to reduce in-band phase noise. However, because of the subsampling characteristic, the demand for capacitor on the loop filter is even greater. In order to avoid the loss and cost of extra area, the traditional capacitor can be replaced by the current-controlled ring-oscillator for storing phase through based on time integrator technology, so a lot of area can be saved. This chip is operated 1.8V power supply, the power consumption is 10.1mW, its core circuit area is about 0.024mm2, when the input reference frequency is 150MHz, the out-put frequency is 2.4GHz. The phase noise performance is-104.1dBc/Hz at 1-MHz frequency offset, and the reference spur is-37.84dBc. ? 2021 IEEE.current-controlled ring-oscillator (CCRO)phase-locked loop (PLL)small areasub-samplingFrequency allocationLocks (fasteners)Phase noiseCurrent controlled ring oscillatorsCurrent-controled ring-oscillatorLoop filterPhase-locked loopRing oscillatorSampling phasisSampling-basedSmall areaSub-samplingTime basedPhase locked loops[SDGs]SDG7conference paper10.1109/RFIT52905.2021.95652852-s2.0-85118189503