FPGA-Based Subset Sum Delay Lines

C.-Y. WangY.-Y. ChenJ.-L. HuangX.-L. HuangJIUN-LANG HUANG2018-09-102018-09-102014-01http://scholars.lib.ntu.edu.tw/handle/123456789/388845[SDGs]SDG7FPGA-Based Subset Sum Delay Linesconference paper10.1109/ATS.2014.602-s2.0-84920051772