張時中臺灣大學:電機工程學研究所蘇方翔Su, Fang-HsiangFang-HsiangSu2010-07-012018-07-062010-07-012018-07-062008U0001-2407200814502600http://ntur.lib.ntu.edu.tw//handle/246246/187947在工程鏈管理中,快速的良率提升(Yield enhancement)是ㄧ關鍵性的面向。在次波長的晶圓製造紀元,高額的投資、市場需求的快速變遷,加上日益複雜的晶圓製造流程,機台與操作,使得半導體廠對於晶圓製造的週期時間需求也是越加的迫切。快速的良率提升是基於有效的良率分析(Yield analysis)知識管理。半導體廠以軟體供應商所提供的工程資料分析(Engineering Data Analysis, EDA)平台為基礎,加入專家知識開發並提供該廠特殊的分析工具,協助工程師進行良率分析。在半導體廠中造成良率分析效率不同的分野在於良率分析流程(Yield analysis procedure, YAP)中,工程師們結合個人獨有的知識與智慧使用工程資料分析工具分析解決問題。率分析流程包含了三個層次: 當有良率分析事件促使工程師產生想要達成的目標且開始產生分析意圖(意圖層)。接下來工程師依據自己的分析意圖去尋找適合的分析工具病診斷錯誤徵兆(分析工具層)。而分析工具的提供來自於第三層:工程資料平台。雖然現有的工程資料分析平台提供了豐富的分析工具,但是良率分析流程知識目前大部分存在於工程師的腦中或是分散的文件中,並沒有被系統化的萃取與記錄在工程資料分析平台。本論文以錯誤徵兆判別作為我們研究的載具問題,研究著重在設計機制,進行分析工具使用流程與錯誤徵兆診斷知識萃取,以達到知識的分享與重複使用,進而提高良率分析的效率。機制設計的挑戰如下: (1)如何依據工程師的分析意圖聯結適當的分析工具供使用?(2)在現存可取得的資料中,如何萃取內隱的且工程師慣用的分析工具流程?(3)如何抓取與儲存工程師在圖形化介面上察覺的錯誤徵兆?對三個挑戰所分別設計的機制包含以下三個部份:.分析意圖與分析工具間的聯結建置:以統一資源模型(Unified Resource Model, URM)為基礎的工程資料分析工具描述。統一資模型是一個語意網路(semantic web)包含點類型(node type)、點(node)與點聯結(node link)。在半導體製造中,點對應到資料名稱如製程(process)與機台(equipment),而點類型為具有相同性質的點的集合,點聯結則是對應到兩個點之間的關係(relation)。藉由相同的統一資源模型基礎語意,來建置工程師意圖與工程資料分析工具間的聯結。.由歷史資料進行分析工具的應用流程與意圖知識萃取: 以馬可夫鏈(Markov chain)為基礎的流程知識萃取演算法(MCPKE)設計。藉由將分析工具視為一個狀態(state)、使用工具序列視為狀態轉移(state transition)、轉移機率(transition probability)視為工程師的偏好(preference)、分析流程視為一個馬可夫鏈,來設計了一個演算法,從歷史的事件登錄資料(event log data)去萃取工程師的流程分析知識。藉由統一資源模型基礎的聯結,流程分析知識可以輔助萃取工程師的意圖知識。.無負擔的錯誤徵兆判別知識萃取: 圖形到文字的錯誤徵兆抓取器 (Graphic-to-text implicit symptom capturer)。為了抓取工程師在圖形化的使用者介面(graphic user interface)上所觀察到的錯誤徵兆,且不增加額外填寫報告的負擔,我們設計了圖形化錯誤徵兆抓取器,可以讓工程師直接在圖形化介面上選取他/她所觀察到的錯誤徵兆。藉由一個軟體的翻譯程式(software interpreter)被選取的錯誤徵兆會被翻譯成文字化的描述,以供儲存與分享。了展現我們的知識萃取機制的可行性,我們實作了一個服務導向架構(Service Oriented Architecture, SOA)為基礎概念性工程資料分析平台,並將所設計的機制整合於其中。藉由我們設計的知識萃取機制,該平台功能的增進如下:.重複使用且分享工程資料分析的流程知識且不增加工程師文件化知識的負擔。.藉由統一資源模型基礎的聯結,減少依意圖去尋找工程資料分析工具的時間。.由MCPKE演算法與統一資源模型萃取分析工具流程知識,並輔助萃取工程師意圖規劃知識。.自動化的轉換工程師所觀察到的圖形化錯誤徵兆到文字化的徵兆描述。Quick yield enhancement is one of the critical aspects of engineering chain management. In the sub-wavelength era, cycle time requirement becomes more stringent because capital investment is sky rocketing while market demands change more rapidly and the manufacturing process, equipments and operations become more complicated than before. Fast yield ramping is founded on effective management of knowledge intensive yield analysis. Semiconductor fabs adopt engineering data analysis (EDA) platforms provided by vendors as basis to develop fab specific analysis function tool suite with domain expert knowledge to assist engineers in yield analysis. What further differentiate the effectiveness of yield analysis among fabs are the yield analysis procedures (YAPs) that engineers combine their knowledge with the applications of the EDA tools for problem solving. AP consists of three layers: Triggered by a yield analysis event, an engineer generates analysis purposes and the corresponding plan (Purpose layer), and then selects and applies appropriate EDA tools in sequence (Tool layer) and identify fault symptoms of EDA tool output to perform analysis according to the purpose plan to accomplish his/her goal. EDA tool provision is by the third layer, EDA platform. In spite of rich tool suites provided by current EDA platforms, YAP knowledge is largely in engineers’ brains or in disparate documentation; they have not been systematically extracted neither stored in EDA system. In this thesis, we use symptom identification as the conveyor problem, the research focuses on mechanism designs to extract EDA tool application procedure and fault symptom identification knowledge for sharing and reusing to achieve more effective yield analysis. Specific design challenges are as follows: (1) How to provide applicable EDA tools by engineers’ specified analysis purposes? (2) How to extract implicit engineers’ preferences of EDA tool application procedures from currently available data? (3) How to capture and store perceived graphic symptoms by engineers and store them? hree mechanisms are designed to conquer these challenges respectively as follow:. Establishment of linkage between analysis purpose and EDA tool: nified Resource Model based EDA tool description. URM is a semantic network consisting of node types, nodes and node links. In the context of semiconductor manufacturing, nodes correspond to data names like process and equipment, etc, while the nodes which have the same property are classified into a node type. Node link corresponds to the relation between two nodes. The linkage between purposes and EDA tools is constructed by matching their semantic meaning in URM terms.. Extraction of EDA tool procedure and purpose knowledge from empirical data: arkov Chain based procedure knowledge extraction algorithm (MCPKE). By modeling an EDA tool as a state, the sequential tool applications as state transitions and the state transition probabilities as engineers’ preferences, the analysis procedures of applying EDA tools are modeled as a Markov Chain, MCPKE algorithm has been developed to extract the process knowledge from empirical event log data. In conjunction with the URM-based linkage, EDA procedure knowledge is then exploited to extract engineers’ purpose plans that drive the application procedures.. Symptom identification knowledge extraction through extra effort free interface: raphic-to-text implicit symptom capturer (GSC). To capture engineers’ observed fault symptoms through the graphic user interfaces they use daily without requiring extra reporting efforts, a graphic symptom capturer technique is designed that enables an engineer to directly select the symptom pattern he/she perceives over the graphic charts. The graphic symptom pattern is then translated into text descriptions by a design of software interpreter for knowledge storage and sharing. To reveal the knowledge extraction mechanisms which are achievable, we implement a Service Oriented Architecture (SOA) based EDA platform and integrate the mechanisms on it. The four main values of the platform are enhanced by the knowledge extraction mechanisms as follow:. Reuse and sharing of EDA tool procedure knowledge without extra documentation efforts,. Reduction of cycle time from specified purpose to identified EDA tool via URM-based linkage, . Extract EDA tool application procedure knowledge via MCPKE algorithm and URM, and enhance engineers’ purpose plan knowledge extraction,. Automatically translate graphic symptoms which engineers observed to symptom texts by GSC.摘要 ibstract iiiontents vist of Figures viiist of Tables ixhapter 1 Introduction of Semiconductor Manufacturing 1 1.1 Challenges and Significance of Yield Analysis 1 1.2 Literature Survey 3 1.3 Scope of Research 4 1.4 Thesis Organization 6hapter 2 Yield Analysis 7 2.1 Yield Analysis Overview 8 2.1.1 Purpose of Yield Analysis 8 2.1.2 Baseline Procedure of Purpose and EDA Tool/Function Level 10 2.1.3 Information System and Tool 11 2.2 Current Practice of Analysis Tool Application 13 2.3 Features and Needs of Engineering Data Analysis 15 2.4 Challenges of Engineering Data Analysis Knowledge Engineering 17hapter 3 EDA Tool/Function Application Procedure Knowledge Model and Extraction Algorithm 19 3.1 EDA Tool/Function Description via Unified Resource Model 20 3.2 Markov Chain Based Procedure Knowledge Extraction 23 3.2.1 Knowledge Representation Model 23 3.2.2 Knowledge Extraction Algorithm 24 3.3 Purpose Knowledge Extraction 28 3.3.1 Construction of Purpose Planning Tree 28 3.3.2 Branch Filtering of Purpose Planning Tree 30hapter 4 Symptom Identification Knowledge Extraction via Graphic Capturer 32 4.1 Graphic Element Analysis of Charts 33 4.2 URM Based Symptom Description Language Design 35 4.2.1 Symptom Vocabulary 36 4.2.2 Symptom Syntax 38 4.3 Graphic-to-text Implicit Symptom Capturer 42 4.4 Situation-action knowledge Extraction 46 4.5 Summary 48hapter 5 Validation and Enrichment of EDA Platform 49 5.1 Proof-of-Concept Implementation into an EDA Platform 50 5.2 Potential Applications and Preliminary Validation 51 5.3 Summary 57hapter 6 Conclusion and Future Work 59ibliography 622681604 bytesapplication/pdfen-US良率分析工程資料分析馬可夫鏈錯誤徵兆判別智慧型製造電子化診斷Yield AnalysisEngineering Data AnalysisMarkov ChainFault Symptom IdentificationIntelligent Manufacturinge-Diagnostics半導體良率分析知識工程:工具應用及錯誤徵兆判斷Knowledge Engineering for Semiconductor Yield Analysis: Tool Application and Fault Symptom Identificationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/187947/1/ntu-97-R95921060-1.pdf