Dept. of Electr. Eng., National Taiwan Univ.Chang, Hao-ChiehHao-ChiehChangChang, Yung-ChiYung-ChiChangTsai, Yuan-BinYuan-BinTsaiFan, Chih-PengChih-PengFanLIANG-GEE CHEN2007-04-192018-07-062007-04-192018-07-062000-0502714310http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021464https://www.scopus.com/inward/record.uri?eid=2-s2.0-85122276757&doi=10.1109%2fISCAS.2000.856289&partnerID=40&md5=a8106df2eea9c573a27edcca207fa0fbIn this paper, the hardware-oriented structure analysis and an efficient and flexible bitstream parser for MPEG-4 video are presented. The analysis of bitstream structure explores processing requirement and design constraint for bitstream-level processing. The proposed architecture is basically RAM-based that can be reconfigured for various applications. For high bitrate as about 40 Mbit/s, it needs only about 19 MIPS to parse the bitstream. The impact of the proposed architecture on MPEG-4 video is to enhance and extend the processing for bit domain translation and related real time applications.application/pdf363674 bytesapplication/pdfen-USComputer architecture; Constraint theory; Random access storage; Standards; Bitstream structure analysis; Motion picture experts group (MPEG); Image codingjournal article10.1109/ISCAS.2000.8562892-s2.0-85122276757http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021464/1/00856289.pdf