國立臺灣大學電機工程學系暨研究所汪重光2006-07-252018-07-062006-07-252018-07-061999-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7713本文介紹一傳統相鎖迴路之頻率合成器之改 良型架構, 用以降低輸出之相位雜訊並達加速收 斂的效果。整個架構包含相位偵測器, 迴路濾波器, 壓控振盪器及除頻器, 除此之外, 另有一取樣降頻 的機制取代部分的除頻器, 達到降低相位雜訊的 目的。此次針對PHS 系統之設計, 輸出頻帶為 1.655~1.678GHz, 77 個頻道, 頻道間距為300KHz。 模擬結果顯示該此新架構可達200kHz 穩態回路頻 寬, 18us 之快速頻道切換時間, 並比傳統架構提 供額外10dB 相位雜訊的衰減, 而電路功率消耗為 40mW。整顆晶片是利用0.6um N-well SPTM CMOS 製程製作, 晶片面積僅1.9mm2。This project proposes a modified frequency synthesizer architecture to improve the phase noise and convergence speed of the traditional PLL-based one. The whole architecture includes phase detector, loop filter, VCO, and frequency divider. Besides, there is a sub-sampling scheme substituting for parts of the divider to reduce phase noise. The design aims at the PHS standard whose requirements are 1.655~1.678GHz, 77 channels, and 300kHz channel spacing. The simulation results show that this new architecture can achieve 200kHz loop bandwidth, 18us switching time, 10dB phase noise improvement and 40mW power dissipation. The circuit is implemented by SPTM 0.6um N-well CMOS technology, occupying chip area of 1.9 mm2.application/pdf94135 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所相鎖迴路頻率合成器相位偵測器迴路濾波器壓控振盪器除頻器取樣降頻PHS 系統PLLfrequency synthesizerphase detectorloop filterVCOdividersub-samplingPHSreporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7713/1/882215E002041.pdf