國立臺灣大學應用力學研究所郭茂坤2006-07-262018-06-292006-07-262018-06-292003-07-31http://ntur.lib.ntu.edu.tw//handle/246246/21673電子構裝技術是國內電子工業界亟需發展的技術。在輕、薄、短、小、 以及低成本的產業潮流帶動下，新一代的電子構裝技術中，以覆晶構裝以及 晶圓構裝兩大技術最具發展潛力。 在覆晶構裝技術中，由於晶片與基材間的熱膨脹係數相差過多，常須於晶片與 基材間除錫球外另灌入底填膠。而底填膠與基材間以及填充料與晶片間的黏著性足 夠與否，直接影響到電子元件的耐久性及可靠度。 本計畫同時配合理論分析、數值模擬及實驗量測，以探討底填膠與基材間黏著 力的相關問題。計畫中由破壞力學的觀點著手，牽涉到基材及底填膠兩個力學性 質、熱力學性質完全不同的材料、以及界面破壞力學理論等課題。Electronic packaging is a very important technology in domestic microelectronics industry. On the requirement of being light, thin, short, small and low cost, flip-chip packaging is one of most promising techniques. Underfill is a must in the flip-chip packaging in order to compensate stresses arising from the mismatch of CTE (coefficient of thermal expansion) between die and substrate. Consequently, interfacial adhesions, between underfill and substrate as well as between underfill and die, are crucial factors on reliability issues of packaging. In this report, theoretical analysis, numerical modeling and experimental measurement are combined to investigate mechanical properties of underfill and interfacial adhesions.application/pdf172663 bytesapplication/pdfzh-TW國立臺灣大學應用力學研究所覆晶構裝界面黏著度熱膨脹係數底填膠界面裂縫能量釋放率Flip chipinterface adhesioncoefficient of thermal expansionunderfillinterface crackenergy release ratereporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/21673/1/912212E002047.pdf