電機資訊學院: 電子工程學研究所指導教授: 郭斯彥李厚均Lee, Hou-ChunHou-ChunLee2017-03-062018-07-102017-03-062018-07-102015http://ntur.lib.ntu.edu.tw//handle/246246/276688在超大型積體電路10奈米以下的製程中，極紫外光 (EUV)被視為是下一個可能成功的技術之一，然而，在製造EUV基板的時候，只要有些微的雜質掉在基板上即會產生凹凸不平之表面，此種不平的表面稱為基板缺陷。這些缺陷將會影響電路之正確性，由於現有科技的限制，目前尚未能製造出完美無瑕之基板。為了能達到大量生產之標準，移動電路圖常被用來減緩這個問題。雖然現在已經有許多論文探討此問題，但所使用的方法還有許多改善的空間。 本論文將電路圖以及基板各視為影像圖，並利用四元樹來建構空間中相對之位置，之後，在將影像位置進行二位元交錯之編碼。此方法可快速存取四元樹之節點並加速重置演算法之流程。相較於最先進的重置演算法，我們提出的演算法能在較短的時間內得到解答，並得到較佳的位置。In sub-10 nm node VLSI technologies, extreme ultraviolet lithography (EUV) is regarded as one of the promising technologies. However, when producing the EUV mask blanks, even tiny dirt fallen on blanks would finally cause blank''s surface rough, which are called defects. These defects would affect circuit correctness. Due to current technology limitations, there are no defect-free blanks by now. In order to achieve mass production, relocating layouts is commonly used to mitigate the problem. Although there are many works discussing this issue, it is still desirable to achieve better results for better solutions. In this thesis, we regard layouts and blanks as images and use quadtrees to model relative positions. Then, we encode image block locations by interleaving x and y coordinates in binary. This encoding method can fast access nodes in quadtrees and accelerates the overall EUV relocation algorithm. Compared with state-of-the art studies, our algorithm can achieve faster running time and better quality.1212904 bytesapplication/pdf論文公開時間: 2020/8/20論文使用權限: 同意有償授權(權利金給回饋學校)極紫外光基板基板缺陷電路圖基板匹配Physical DesignDesign for ManucacturabilityEUVBlank Defect MitigationMask PreparationDesign Blank Matchingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/276688/1/ntu-104-R02943085-1.pdf