呂良鴻臺灣大學:電子工程學研究所黎信志Li, Sin-JhihSin-JhihLi2010-07-142018-07-102010-07-142018-07-102008U0001-2508200816302900http://ntur.lib.ntu.edu.tw//handle/246246/189038本篇論文主題主要在介紹高頻鎖相迴路的設計與實作。論文中討論了數個方法以改善在高頻鎖相迴路中時脈擾動的情形。論文共分為六個章節，首先第一章對此篇論文作概略性的介紹，第二章則回顧鎖相迴路的背景知識。三章提出了一個使用多重相位控制的鎖相迴路架構。藉由此架構可有效抑制壓控震盪器控制電壓上來自參考時脈的週期性擾動，進而減少時脈鎖定時的擾動現象。此迴路架構使用了0.18-μm標準互補式金氧半導體製程加以實現，同時量測結果也會於本章呈現。四章將實現一個雙迴路的鎖相迴路架構。此架構可等效上減少迴路濾波器所需要的電容面積，故有助於單晶積體電路的整合。由於來自晶片外的元件雜訊減少了，時脈鎖定時的雜訊擾動現象也能因此有所改善。此鎖相迴路設計使用了0.18-μm標準互補式金氧半導體製程實作並且加以量測。五章將討論一個30-GHz的鎖相迴路設計。此設計採用了改良式的Colpitts壓控震盪器以減少壓控震盪本身所產生雜訊並使用了regenerative除頻器來增加如此高速下時脈信號的除頻範圍。此章將詳述此30-GHz鎖相迴路之設計流程與模擬結果。This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first chapter is the introduction. In chapter 2, the background knowledge for the PLL design is overviewed.n chapter 3, a PLL with multi-phase control architecture is proposed. Since the proposed architecture effectively suppresses the ripple of the controlled voltage, the jitter resulted from the reference feedthrough is decreased. The circuit is implemented with 0.18-μm CMOS technologies and the measured resulted is also included in this chapter.n chapter 4, a PLL with a compact loop filter is presented. The presented architecture is well suited for the implementation of fully integrated PLLs since the required capacitance in the loop filter can be substantially reduced. The jitter performance will be improved because of the absence of offchip components. The circuit is also realized with 0.18-μm CMOS process and the measured resulted is also included in this chapter.n chapter 5, a PLL operated at 30-GHz is designed and simulated. The modified Colpitts VCO is adopted for the reduction of the VCO noise. A regenerative frequency divider is also employed to widen the dividable range at such high frequency. The design process and the simulation results will be illustrated in this chapter.Acknowledgement........................................Ibstract................................................IIIable of Contents.......................................VIIist of Figures..........................................XIist of Tables...........................................XVHAPTER 1 INTRODUCTION....................................1.1 MOTIVATION............................................1.2 THESIS OVERVIEW.......................................2HAPTER 2 BACKGROUND......................................5.1 BASIC CONCEPTS OF THE PLL.............................5.2 BUIDING BLOCKS OF THE PLL.............................6.2.1 THE PHASE AND FREQUENCY DETECTOR (PFD) AND CHARGE PUMP (CP).................................................6.2.2 VOLTAGE-CONTROLLED OSCILLATOR (VCO).................9.2.3 FREQUENCY DIVIDER (FD).............................10.3 THE LINEAR MODEL FOR THE PLL.........................10.4 JITTER...............................................14HAPTER 3 A LOW-JITTER 10-GHZ PHASE-LOCKED LOOP WITH THE MULTI-PHASE CONTROL......................................17.1 INTRODUCTION.........................................17.2 THE PROPOSED PLL ARCHITECTURE........................19.2.1 DISTRIBUTED PFD AND CP WITH MULTI-PHASE CONTROL....20.2.2 DECOMPOSITION OF FREQUENCY AND PHASE DETECTION.....23.3 CIRCUIT IMPLEMENTATION...............................25.4 EXPERIMENTAL RESULTS.................................29.5 CONCLUSION...........................................32HAPTER 4 A 10-GHZ PHASE-LOCKED LOOP WITH A COMPACT LOOP FILTER...................................................35.1 INTRODUCTION.........................................36.2 THE PROPOSED PLL ARCHITETURE.........................37.2.1 COMPACT-LOOP-FILTER TECHNIQUE......................37.2.2 PD/FD DECOMPOSTION.................................41.2.3 DESIGN TRADEOFF....................................43.3 CIRCUIT IMPLEMENTATION...............................45.4 EXPERIMENTAL RESULTS.................................49.5 CONCLUSION...........................................52HAPTER 5 A 30-GHZ PHASE-LOCKED LOOP.....................53.1 INTRODUCTION.........................................53.2 ARCHITECTURE.........................................54.3 CIRCUIT IMPLEMENTATION...............................55.3.1 THE MODIFIED COLPITTS VCO..........................55.3.2 REGENERATIVE FREQUENCY DIVIDER.....................57.4 SIMULATION RESULTS...................................59.4.1 THE BEHAVIOR MODEL SIMULATION......................59.4.2 THE MODIFIED COLPITTS VCO AND THE REGENERATIVE FREQUENCY DIVIDER...........................61.5 CONCLUSION...........................................62HAPTER 6 CONCLUSION.....................................65IBLIOGRAPHY.............................................671473445 bytesapplication/pdfen-US高頻鎖相迴路頻率偵測器多相位控制Phase-locked loopPDFDmulti-phased controlthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189038/1/ntu-97-R95943026-1.pdf