Chen, T.-W.T.-W.ChenSun, C.-H.C.-H.SunSu, H.-H.H.-H.SuChien, S.-Y.S.-Y.ChienDeguchi, D.D.DeguchiIde, I.I.IdeMurase, H.H.MuraseSHAO-YI CHIEN2018-09-102018-09-102011http://www.scopus.com/inward/record.url?eid=2-s2.0-81255134140&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/365125A power-efficient K-Means hardware architecture that can automatically estimate the number of clusters in the clustering process is proposed. The contributions of this work include two main aspects. The first is the integration of the hierarchical data sampling in the hardware to accelerate the clustering speed. The second is the development of the Bayesian-Information- Criterion (BIC) Processor to estimate the number of clusters of K-Means. The architecture of the BIC Processor is designed based on the simplification of the BIC computations, and the precision of the logarithm function is also analyzed. The experiments show that the proposed architecture can be employed in different multimedia applications, such as motion segmentation and edge-adaptive noise reduction. Besides, the gate count of the hardware is 51 K with the 90-nm complimentary metal-oxide-semiconductor technology. It is also shown that this work can achieve high efficiency compared with a GPU, and the power consumption scales well with the number of clusters and the number of dimensions. The power consumption ranges between 10.72 and 12.95 mW in different modes when the operating frequency is 233 MHz. © 2011 IEEE.Clustering methods; energy efficiency; hardware design; K-Means; machine learning[SDGs]SDG7Clustering methods; Clustering process; Complimentary metal oxide semiconductors; Different modes; Gate count; Hardware architecture; hardware design; Hierarchical data; K-means; K-means clustering; Logarithm function; Machine-learning; Motion segmentation; Multimedia applications; Multimedia processing; Number of clusters; Operating frequency; Power efficient; Proposed architectures; Clustering algorithms; Energy efficiency; Hardware; MOS devices; Semiconductor device manufacture; Computer architecturejournal article10.1109/JETCAS.2011.2165231