指導教授：劉深淵臺灣大學：電子工程學研究所曾凱暉Tseng, Kai-HuiKai-HuiTseng2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263894這篇論文的主題主要分為二個部分，第一個部分提出一個具有自我校正注入點之無除頻器次諧波注入鎖定全數位鎖相迴路。採用次諧波注入鎖定技巧來壓抑全數位鎖相迴路的相位雜訊。此全數位鎖相迴路不使用耗功率的時間數位轉換器，而是使用砰砰相位偵測器來達成。為了達到低功耗，全數位鎖相迴路的除頻器和三角積分器可以自動的被關閉。此論文提出一種自我校正次諧波注入時機的機制，以達到良好的相位誤差，並分析次諧波注入鎖定相位雜訊與量測做比較。此全數位鎖相迴路使用40奈米製程製做。在電源1.1伏特下消耗的功率為3.07毫瓦。量測到的相位雜訊在1MHz之頻率偏移為–121.94 dBc/Hz。從頻率偏移1kHz積分到100MHz所得到的方均根抖動為109.4fs。計算的FOM指標為–254.35 dB。 第二部分提出一個頻率追鎖的方法，砰砰相位偵測器直採樣全數位鎖相迴路的輸出，而不用透過任何除頻器。無論在頻率追鎖或相位追鎖，全數位鎖相迴路皆使用砰砰相位偵測器來達成，而非傳統的時間數位轉換器，並使用自我校正注入點的技巧，全數位鎖相迴路在製程、電壓、溫度變異下皆能保持良好的相位雜訊。此全數位鎖相迴路使用40奈米製程製做。在電源1.1伏特下消耗的功率為3.04毫瓦。量測到的相位雜訊在1MHz之頻率偏移為–121.4 dBc/Hz。從頻率偏移1kHz積分到100MHz所得到的方均根抖動為109.6fs。計算的FOM指標為 –254.39 dB。This thesis consists of two parts. A Divider-Less Sub-Harmonically Injection-Locked All-Digital PLL with Self-Adjusted Injection Timing is proposed in the first part. The sub-harmonically injection-locked technique is adopted to suppress ADPLL phase noise. This ADPLL works with BBPD instead of power-consuming time to digital converter. To lower the power, the dividers and the DSM of this ADPLL are automatically turned off. A self-adjust injection timing technique is proposed in this work to achieve good phase noise and analysis the sub-harmonically injection-locked phase noise model and compares with measurement. This ADPLL is fabricated in a 40nm CMOS technology. Its power consumption is 3.07mW for a supply voltage of 1.1 V. The measured phase noise is equal to –121.94 dBc/Hz at an offset frequency of 1MHz. The integrated rms jitter is 109.4 fs for the offset frequency from 1kHz to 100MHz. The calculated figure-of-merit is equal to –254.35 dB. A frequency acquisition technique is proposed in the second part. The BBPD samples the output of the ADPLL directly without though any divider loop. This ADPLL uses only a simple bang-bang phase detector without time-to-digital converter when both frequency and phase locking. In addition, the self-adjust injection timing technique is utilized. The ADPLL keeps good phase noise against PVT variation. This ADPLL is fabricated in a 40nm CMOS technology. Its power consumption is 3.04mW for a supply voltage of 1.1 V. The measured phase noise is equal to –121.4 dBc/Hz at an offset frequency of 1MHz. The integrated rms jitter is 109.6 fs for the offset frequency from 1kHz to 100MHz. The calculated figure-of-merit is equal to –254.39 dB.Chapter 1 Introduction 1 1.1 Wireline Communication 1 1.2 Overview 2 Chapter 2 A Divider-Less Sub-Harmonically Injection-Locked All-Digital PLL with Self-Adjusted Injection Timing 3 2.1 Motivation 3 2.2 Circuit Description 5 2.2.1 ADPLL 5 2.2.2 The Proposed Lock Detector 6 2.2.3 The Proposed Pulse Generator 7 2.2.4 The Digital-Controlled Oscillator 8 2.2.5 The BBPFD and BBPD 9 2.3 Performance Analysis 10 2.3.1 Phase Noise Analysis 10 2.4 Measurement Results 13 2.5 Summary and Conclusions 17 3. A Truly Divider-Less Sub-Harmonically Injection-Locked All-Digital PLL with Self-Adjusted Injection Timing 20 3.1 Motivation 20 3.2 Circuit Description 22 3.2.1 The Frequency Acquisition Algorism 22 3.2.2 ADPLL 30 3.2.3 The Proposed PG 31 3.3.4 The DCO 32 3.3 Measurement Results 33 3.4 Summary and Conclusions 37 4. Conclusion and Future Work 40 4.1 Conclusion 40 4.2 Future Work 41 Bibliography 421704433 bytesapplication/pdf論文使用權限：不同意授權無除頻器全數位鎖相迴路thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263894/1/ntu-103-R00943048-1.pdf