2015-08-012024-05-18https://scholars.lib.ntu.edu.tw/handle/123456789/703164摘要：下世代行動通訊，將要提升最高使用者速率至1 Gigabit per Second (Gbps) 。這個新的速率需求，使得基地台的涵蓋範圍要縮小，減輕基地台回傳的速率瓶頸，同時基地台數量將增加十倍以上，而且要提高發射頻率至毫米波段，以增加可用的頻寬。因此，對於功率放大器的輸出功率要求將要降低，而且價格也需要降低。本計劃將使用CMOS製程來研發行動通訊的功率放大器，雖然CMOS製程的輸出功率較現有的GaAs製程為低，但是符合未來行動通訊的需求，也可以降低放大器的成本。 本計劃將開發下世代行動通訊的功率放大器。利用不同的功率合成架構，將CMOS製程有限的功率輸出，合成為接近於瓦級(Watt-level)的大輸出功率。功率合成架構不只要考慮提供同相位的功率合成，還要考慮功率電晶體的最佳阻抗匹配。最後還要考慮在多路功率合成中，如何安排一次合成或是分階段合成，來達到最小面積的多路功率合成。這縮小面積的設計不僅可以減少損耗，也可以降低晶片的成本，符合下世代行動通訊低耗電低成本的設計目標。 <br> Abstract: For next-generation mobile communications, the user experience of data rate will be increased up to 1 Gbps. This new speed requirement will have small-cell base-stations to mitigate the speed bottleneck of next-generation mobile backhaul transmission. In the same way, the number of base-stations will be increased 10 times, and the operation frequency will be increased to millimeter-wave bands for wider bandwidth. Therefore, the next-generation power amplifiers will have lower output power requirement and lower cost. This project will develop the next-generation power amplifiers using the CMOS process. Although CMOS has lower output power than the current GaAs process, low power and low cost are the trend of the next-generation mobile devices. This project will design and fabricate the next-generation power amplifiers using the CMOS process. The power combining techniques will be developed to combine CMOS devices to achieve watt-level output power. The power combining techniques will consider the in-phase combining, the optimal impedance matching, and the minimum chip area of N-way power combiner. The miniature N-way combiner design can reduce the loss of combiner, and also reduce the cost of CMOS chip, which are the design targets of next-generation mobile power amplifiers.功率放大器CMOS多路功率合成Power AmplifierCMOSN-way Power Combining