臺灣大學: 電子工程學研究所盧信嘉黃紹華Huang, Shao-HuaShao-HuaHuang2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/256878本篇論文提供了將電路佈局圖轉換為電路圖之方法。內容可分為兩部分，佈局圖的分割與元件擷取。第一部分對佈局圖分割出可能構成元件的矩形，配合使用者定義的設計規則，將矩形分類為可能構成電感的部份與可能構成電容的部分。第二部分是從分割得到的矩形中依照元件的幾何特性擷取出元件，並依照佈局圖的連結方式將元件連結，得到電路圖。此對應佈局圖之電路圖可和設計者提供的電路圖做比對檢查，進行電路設計的偵錯。此兩部分為佈局圖對電路檢查之前段作業。 此方法實際使用在四個LTCC及BCB製程的微波電路佈局圖上，確實可以正確的產生出對應的電路圖。This thesis presents a method that can generate schematic from layout of passive microwave multi-layer circuit. There are two parts in this thesis. The first part is about dividing the rectilinear polygon into rectangles that may constitute capacitors and inductors. With user-defined design parameters such as maximum line width and minimum line width, we can classify the rectangles that may be part of a capacitor or a inductor. The second part is about extracting component according to the geometric characteristics of the components. Schematic is then generated according to the connectivities of extracted components in the layout. Designers can then compare the schematic corresponding to the layout with the original schematic for debugging. These two parts are the front-end of layout vs. schematic (LVS) checker. We implement this method and test it in layouts using LTCC and BCB processes. It can indeed generate the correct schematics from layouts.3265116 bytesapplication/pdfen-US佈局圖佈局圖對電路圖檢查直線多邊形計算幾何layoutLVSrectilinearcomputational geometrythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256878/1/ntu-99-R97943146-1.pdf