臺灣大學: 電子工程學研究所張耀文鄭仲鈞Cheng, Chung-ChunChung-ChunCheng2013-04-102018-07-102013-04-102018-07-102009http://ntur.lib.ntu.edu.tw//handle/246246/256949140 bytestext/htmlen-US時鐘樹障礙物迴避控制電壓迴轉率製程變異容忍緩衝器插入Physical DesignClock TreeBlockage AvoidanceSlew RateVariation ToleranceBuffer Insertion考慮障礙物及緩衝器之時脈訊號延遲範圍最小化時鐘樹合成Blockage-Avoiding Buffered Clock-Tree Synthesis with Clock Latency-Range Minimizationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256949/1/index.html