Qian Y.CChao Y.-YSHEN-IUAN LIU2021-09-022021-09-022019https://www.scopus.com/inward/record.uri?eid=2-s2.0-85083643592&doi=10.1109%2fA-SSCC47793.2019.9056927&partnerID=40&md5=f7a266ee520de2cc6e29574a5e6320aahttps://scholars.lib.ntu.edu.tw/handle/123456789/581133A sub-sampling phase-locked loop (SSPLL) is presented to tolerate the supply interference and have a short re-locking time. A sampling phase detector, a voltage-to-current converter and a mini-dead zone creator are presented. The low in-band phase noise of the proposed SSPLL is kept and the power penalty is low. This SSPLL is realized in a 0.18μm CMOS process and its active area is 0.097mm2. The power consumption is 13.59mW from a 1.8V supply. At the output frequency of 2.2 GHz, this SSPLL achieves an in-band phase noise of-115.33dBc/Hz at 100kHz offset frequency with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 0.77 ps. ? 2019 IEEE.[SDGs]SDG7Locks (fasteners); Phase locked loops; Phase noise; In-band phase noise; Offset frequencies; Output frequency; Power penalty; Robust operation; Root mean square jitter; Sampling phase detector; Voltage-to-current converters; Phase comparatorsconference paper10.1109/A-SSCC47793.2019.90569272-s2.0-85083643592