Huang, C.-C.C.-C.HuangTseng, K.-W.K.-W.TsengSHEN-IUAN LIU2020-06-112020-06-112016https://scholars.lib.ntu.edu.tw/handle/123456789/499875https://www.scopus.com/inward/record.uri?eid=2-s2.0-84994779298&doi=10.1109%2fRFIT.2016.7578178&partnerID=40&md5=ecbb7a180c952c10719727e250e9e38bA 10-20 Gb/s clock and data recovery (CDR) circuit with frequency tracking is presented. Two digital phase interpolators (PIs) are used to track the frequency of input data. The loop bandwidth of the CDR circuit is adaptively adjusted. A mixed-mode PI is used to generate the recovered clock. This CDR circuit is fabricated in a 40nm CMOS process and its area is 0.33×1.0 mm2. Its power consumption is 97.2mW with a supply voltage of 1.5V. This CDR circuit can track the data with the down spread-spectrum clocking of 6200ppm for a 20Gb/s pseudo random binary sequence (PRBS) of 27-1, when the bit-error rate is less than 10-12. The measured rms jitters of the retimed data are 2.78ps and 2.33ps for the data of 10Gb/s and 20Gb/s, respectively. © 2016 IEEE.clock and data recovery (CDR); mixed-mode; phase interpolator (PI); spread-spectrum clocking (SSC)[SDGs]SDG7Binary sequences; Bit error rate; Clocks; Interpolation; Radio waves; Reconfigurable hardware; Recovery; Spectroscopy; Timing circuits; Clock and data recovery; Frequency tracking; Loop bandwidth; Mixed mode; Phase interpolator; Pseudo-random binary sequences; Spread spectrum clocking; Supply voltages; Clock and data recovery circuits (CDR circuits)conference paper10.1109/RFIT.2016.75781782-s2.0-84994779298