李建模Li, Chien-Mo James臺灣大學:電子工程學研究所許肇軒Hsu, Chao-HsuanChao-HsuanHsu2010-07-142018-07-102010-07-142018-07-102009U0001-1307200912474500http://ntur.lib.ntu.edu.tw//handle/246246/189235薄膜電晶體有越來越多的應用在大面積、軟性電子電路以及可印刷式電子電路上。而在軟性電子電路方面，由於軟性基板在經過不同方向的撓曲後，會造成軟性電子電路的電器特性受到改變，尤其是電路的mobility將會嚴重的變化，進而造成電路無法正常工作，所以撓曲對軟性電子電路是一個非常重要且值得探討的課題。這個研究提出了一套軟性電子電路上的電子自動化軟體，針對軟性電子電路之靜態時序分析(STAF)，STAF的目的為分析軟性電子電路經過撓曲後的電器特性改變。而在STAF的分析ISCAS’89電路的模擬結果顯示，最大的最長路徑延遲(longest path delay)再經過撓曲後的增加量多出原先32%，而在最大的最短路徑延遲(shortest path delay)再經過撓曲後的減少量少於原先9%。最後我們使用四種類似熱量曲線的地圖去顯示出STAF的分析結果，而這四種地圖可以幫助設計者針對地圖上所標示的對於撓曲最敏感的區域去做電路設計上的修正，用以達到在撓曲的情況下的高可靠性設計。目前為止據我們所知，STAF是第一套針對軟性電子電路的電子自動化軟體。Thin-film transistors (TFTs) technology is widely used in large area, flexible and printed electronics. Due to the compressive or tensile strain, change in mobility is a serious concern for flexible TFT circuits. A static timing analyzer for flexible electronics (STAF) is proposed for flexible TFT circuits under strain. The simulation results of ISCAS’89 benchmark circuits show that the maximum increase in longest path delay is 32% and maximum reduction in shortest path delay is 9%. Four types of maps can be plotted and the “hot spot”, which is the most sensitive to bending, can be identified. So far as we know, STAF is the first design for flexibility EDA tool for flexible TFT electronics.摘要 ibstract iiable of Contents iiiist of Figures vist of Tables ixhapter 1 Introduction 1.1 Motivation 1.2 Proposed Technique 3.3 Contributions 7.4 Organization 7hapter 2 Background 8.1 Amorphous-Silicon Thin-film Transistor 8.1.1 Static Characteristics 8.1.2 Typical designs using a-Si TFTs 11.2 Flexible TFT under strain 13.2.1 A-Si TFT 13.2.2 Polycrystalline silicon TFT and organic TFT 19.3 Static timing analysis 24hapter 3 Proposed technique 27.1 SPICE simulation model of a-Si TFT with bending 28.2 A-Si TFT standard cell library 30.3 STAF implementation 34.4 Error 42.5 Flexibility maps 44hapter 4 Experimental results 48.1 Simulation results of standard cell 48.2 Simulation results of ISCAS’89 benchmark circuits 51.2.1 Simulation results with square bending regions 51.2.2 Simulation results with column bending regions 59.2.3 Simulation results with row bending regions 65.3 Flexibility maps 71.4 CUT design and experimental setup 80.5 Measurement and error of STAF 82hapter 5 Conclusion and Future Work 86eferences 872102095 bytesapplication/pdfen-US可撓性軟性電子撓曲摺疊靜態時序分析flexible electronicsstatic timing analysisbendinglongest path delayshortest path delaythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189235/1/ntu-98-R96943079-1.pdf