Fang, J.P.J.P.FangTong, Y.-S.Y.-S.TongSAO-JIE CHEN2018-09-102018-09-10200413502387http://www.scopus.com/inward/record.url?eid=2-s2.0-1542581484&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/309229An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based between-buffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.[SDGs]SDG11Congestion constraints; Cost functions; Manhattan routing (MR); Algorithms; Approximation theory; Estimation; Graph theory; Matrix algebra; Optimization; Perturbation techniques; Problem solving; Routers; Topology; VLSI circuitsjournal article10.1049/ip-cdt:200400722-s2.0-1542581484