Jung-Yu ChangChe-Wei FanChe-Fu LiangSHEN-IUAN LIU2018-09-102018-09-102009-0215497747http://scholars.lib.ntu.edu.tw/handle/123456789/352066https://www.scopus.com/inward/record.uri?eid=2-s2.0-62749191175&doi=10.1109%2fTCSII.2008.2010181&partnerID=40&md5=4518e1a1c4cf1a7a532759bc16e6fdc3A single phase-locked loop (PLL) frequency synthesizer for a Mode-1 multiband orthogonal frequency-division multiplexing (MB-OFDM) ultrawideband (UWB) system is realized in 0.13-μmu CMOS. A current-reused multiply-by-1.5 circuit and a multiphase coupled ring oscillator are adopted to reduce the power consumption. For a 4.488-GHz signal, the measured image sideband is -40 dBc. The measured switching time from 3.342 to 4.488 GHz is 1.5 ns. The area is 0.85 × 0.9 mm2 and the power is 31.2 mW for a 1.2-V supply voltage. © 2009 IEEE.Current reused; Multiply-by-1.5 circuit; Phase-locked loop (PLL); Ring oscillator; Ultrawideband (UWB)Frequency multiplying circuits; Frequency synthesizers; Orthogonal frequency division multiplexing; Oscillators (electronic); Phase locked loops; Current-reused; Multi-band orthogonal frequency division multiplexing; Phase Locked Loop (PLL); Ring oscillator; Single phase; Supply voltages; Switching time; Ultrawideband systems; Ultra-wideband (UWB)journal article10.1109/TCSII.2008.20101812-s2.0-62749191175WOS:000263919400004