Hsieh, Cheng YunCheng YunHsiehTsai, Hsin YingHsin YingTsaiLu, Yuan HsiangYuan HsiangLuCHIEN-MO LI2024-01-312024-01-312023-01-0102780070https://scholars.lib.ntu.edu.tw/handle/123456789/639422Probabilistic error cancellation (PEC) is a promising error mitigation technique that reduces the error rate without auxiliary qubits. However, PEC has two problems that need to be resolved: (1) There is no good PEC technique for parameterized gates. (2) Sampling overhead grows exponentially with the number of PEC mitigated gates. We first propose a parameterized gate PEC (PGPEC) that mitigates the error without fully characterizing the gates, as the original PEC requires. The result shows that the number of gates requiring characterization for a thousand random circuits can be reduced by 97% or more. We next propose two novel approaches to solving the second problem. We propose a macro gate PEC (MGPEC) technique that aggregates multiple gates as a single macro gate to reduce the exponent of the sampling overhead. MGPEC reduces the sampling overhead by 49% on the QFT7 under the IBMQ noise model, which simulates real operation conditions of quantum circuits. We propose a design diversity PEC (DDPEC) technique to reduce the exponential basis of the sampling overhead. The results show that our DDPEC with design diversity check reduces overall sampling overhead by 13% on the QFT7 circuit under the IBM Q noise model. Combining the DDPEC with the MGPEC, we can reduce overall sampling overhead by 73%.Diamonds | Error mitigation | Logic gates | Noise measurement | Probabilistic error cancellation | Probabilistic logic | Quantum circuit | Quantum circuit | Quantum state | Qubitjournal article10.1109/TCAD.2023.33290422-s2.0-85181563300https://api.elsevier.com/content/abstract/scopus_id/85181563300