Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding

AN-YEU(ANDY) WULin, C.-H.C.-H.LinChen, C.-Y.C.-Y.ChenAN-YEU(ANDY) WU2018-09-102018-09-102011http://www.scopus.com/inward/record.url?eid=2-s2.0-79151477141&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/365389Most of advanced wireless standards, such as WiMAX and LTE, have adopted different convolutional turbo code (CTC) schemes with various block sizes and throughput rates. Thus, a reconfigurable and scalable hardware accelerator for multistandard CTC decoding is necessary. In this paper, we propose scalable maximum a posteriori algorithm (MAP) processor designs which can support both single-binary (SB) and double-binary (DB) CTC decoding, and handle arbitrary block sizes for high throughput CTC decoding. We first propose three combinations of parallel-window (PW) and hybrid-window (HW) MAP decoding. Moreover, the computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve a high area utilization. To verify the proposed approaches, a 1.28 mm2 dual-mode 2PW-1HW MAP processor is implemented in 0.13 μm CMOS process. The prototyping chip achieves a maximum throughput rate of 500 Mb/s at 125 MHz with an energy efficiency of 0.19 nJ/bit and an area efficiency of 3.13 bits/mm2. For the multistandard systems, the expected throughput rates of the WiMAX and LTE CTC schemes is achieved by using five dual-mode 2PW-1HW MAP processors. © 2006 IEEE.Maximum a posteriori algorithm (MAP); multistandard platform; turbo codes[SDGs]SDG7Area efficiency; Area efficient; Area utilization; Block sizes; CMOS processs; Convolutional turbo codes; Dual modes; Expected throughput; High throughput; MAP decoding; Maximum a posteriori algorithm; Maximum through-put; Multi-standard; Multi-standard systems; Processor design; Prototyping; Re-configurable; Scalable hardware; Throughput rate; Turbo decoding; Wireless standards; Algorithms; CMOS integrated circuits; Convolution; Decoding; Energy efficiency; Reconfigurable hardware; Throughput; Wimax; Turbo codesArea-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decodingjournal article10.1109/TVLSI.2009.2032553