Chen, Y.-F.Y.-F.ChenHuang, C.-C.C.-C.HuangChiou, C.-H.C.-H.ChiouWang, C.-J.C.-J.WangYAO-WEN CHANG2018-09-102018-09-1020140738100Xhttp://www.scopus.com/inward/record.url?eid=2-s2.0-84903138338&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/387325We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CPtrees can flexibly pack movable macros toward corners or preplaced macros along chip boundaries circularly to optimize macro positions/orientations for better wirelength and routing congestion. Unlike previous macro placers that often consider only the interconnections among macros, we develop a routability-aware wirelength model to fast estimate the wirelength among macros and standard cells and to consider macro porosity effects for better routability. Compared with leading academic mixed-size placers, experimental results show that our algorithm can achieve the shortest routed wirelength for industrial benchmarks. Copyright 2014 ACM.Physical Design; Placement; Routability[SDGs]SDG11Computer aided design; Chip boundaries; Macro-porosity; Physical design; Placement; Routability; Routing congestion; Standard cell; Wire length; Forestry; Algorithms; Cad Cam; Forestry; Problem Solvingconference paper10.1145/2593069.25932062-s2.0-84903138338