Test time reduction for scan-designed circuits by sliding compatibility

Dept. of Electr. Eng., National Taiwan Univ.Chang, Jau-ShienJau-ShienChangLin, Chen-ShangChen-ShangLin2007-04-192018-07-062007-04-192018-07-061994-11http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032442application/pdf639134 bytesapplication/pdfen-USTest time reduction for scan-designed circuits by sliding compatibilityjournal article10.1109/ATS.1994.367210http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032442/1/00367210.pdf