You-Jen WangShao-Ku KaoSHEN-IUAN LIU2018-09-102018-09-102006-0600189200http://scholars.lib.ntu.edu.tw/handle/123456789/325486https://www.scopus.com/inward/record.uri?eid=2-s2.0-33746587076&doi=10.1109%2fJSSC.2006.874326&partnerID=40&md5=e8234bfd303afde82f388c0636fa4b12An all-digital delay-locked loop (DLL) and an all-digital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the flash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequential time-to-digital conversion is adopted to reduce the required D-flip-flops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cycle is eliminated. The proposed circuits have been fabricated in a 0.35-μm CMOS process. The proposed DLL generates the output clock with the duty cycle of 25%, 50% and 75%, and the operation frequency range is from 140 to 260 MHz. For the proposed PWCL, the duty cycle is adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 to 600 MHz. © 2006 IEEE.Delay-locked loop (DLL); Duty cycle and time-to-digital conversion; Pulsewidth control loop[SDGs]SDG7Delay-locked loop (DLL); Duty cycle and time-to-digital conversion; Input clock; Pulsewidth-control loop (PWCL); Circuit theory; CMOS integrated circuits; Electric clocks; Frequency modulation; Phase locked loops; Digital devicesjournal article10.1109/JSSC.2006.8743262-s2.0-33746587076WOS:000238153800004