2021-01-012024-05-13https://scholars.lib.ntu.edu.tw/handle/123456789/652169為了瞭解高效能的神經網路加速器在物聯網邊緣裝置的應用，此子計畫旨在元件的研究與開發和基於先進CMOS製程下之鐵電場效電晶體的電路技術。藉由和其他兩個子計畫合作，可以檢驗基於鐵電場效電晶體之機器學習神經網路加速器設計。研究抵抗短通道效應之元件設計，且具有陡坡特性、大記憶體視窗、類比電導調變並伴隨著高線性度、高對稱性以及高可靠度的特性。藉由元件-電路協同最佳化對加速器的設計，將提供鐵電場效電晶體的元件設計指引方針。 This subproject aims to conduct research and development of device and circuit technologies of ferroelectric transistor based on advanced CMOS process in order to realize highly energy-efficient neural network accelerator for IoT edge devices. By collaborating with the other two subprojects, the ferroelectric transistor machine learning neural network accelerator design will be examined. The device design study is to be done for high short channel immunity, steep slope characteristics, large memory window, analog conductance modulation with high linearity and symmetry, and high reliability. By device-circuit co-optimization for accelerator design, the design space and guidelines are provided back to FeFET design.鐵電場效電晶體非揮發性記憶體神經網路加速器神經突觸記憶體視窗Ferroelectric FETnon-volatile memoryneural network acceleratorsynapsememory window