陳中平臺灣大學：電子工程學研究所林宗澤Lin, Tsung -TseTsung -TseLin2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57380In this thesis, we propose a method for fast and effective combinational gates and flip-flop sizing using Lagrangian Relaxation (LR) and posynomial model- ing. Our algorithm optimizes a circuits delay subject to slew rate constraints, and can readily take process variation into account. We use Synopsys liberty format technology file to generate accurate delay models in posynomial form for standard cells, and then we parse the input synthesized verilog file. After reading the netlist, we do the re-formulation to represent the paths which start from either primary input or flip-flop. After netlist re-formulation, we have a large-scale, convex optimization problem based on the posynomial models. Finally, we perform LR to solve for the globally-optimal set of tran- sistor sizes for each cell and then we discretize them to the nearest drive strength.1 Introduction 1 1.1 Clock Skew Optimization . . . . . . . . . . . . . . . . . . . . . 1 1.2 Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Background and Motivation 4 2.1 Previous Works on Gate Sizing . . . . . . . . . . . . . . . . . 4 2.2 Previous Works on Leakage Reduction . . . . . . . . . . . . . 5 2.2.1 MTCMOS(Sleep Transistors) . . . . . . . . . . . . . . 6 2.2.2 Multiple Vt Assignment . . . . . . . . . . . . . . . . . . 7 2.3 Motivation of the Thesis Work . . . . . . . . . . . . . . . . . . 7 3 The optimal algorithm for sizing cyclic sequential circuits for industrial library based designs 12 3.1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Notations and Circuit Formulation . . . . . . . . . . . . . . . 13 3.3 Posynomial Functions and Geometric programming . . . . . . 21 3.4 Modelling in Posynomial Form . . . . . . . . . . . . . . . . . . 22 3.5 Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.1 Delay Constraints . . . . . . . . . . . . . . . . . . . . . 26 3.5.2 Setup Time and Hold Time Constraints . . . . . . . . 26 3.6 Posynomial-Based Lagrangian Relaxation . . . . . . . . . . . . 29 3.6.1 Primal Problem Formulation . . . . . . . . . . . . . . . 29 3.6.2 Lagrangian Relaxation . . . . . . . . . . . . . . . . . . 31 3.6.3 KKT Condition for the Lagrangian Function Solution . 33 3.6.4 Iterative Multiplier Adjustment . . . . . . . . . . . . . 37 3.6.5 Solving LRS/lambda . . . . . . . . . . . . . . . . . . . . . . 38 3.6.6 Drive Strength Discretization . . . . . . . . . . . . . . 39 3.7 Experiment Result . . . . . . . . . . . . . . . . . . . . . . . . 41 3.8 Unateness Consideration . . . . . . . . . . . . . . . . . . . . . 41 4 Conclusion 48 Bibliography 49288291 bytesapplication/pdfen-US最佳化gate sizingthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57380/1/ntu-95-R94943147-1.pdf