顧孟愷Ku, Mong-Kai臺灣大學:資訊工程學研究所周書正Chou, Shu-ChengShu-ChengChou2010-06-022018-07-052010-06-022018-07-052008U0001-2907200822012900http://ntur.lib.ntu.edu.tw//handle/246246/184876由於在行動應用裝置中低功率設計的需求愈來愈重要，我們提出了一個降低運算數目的LDPC解碼器演算法。這個演算法能夠減少必須運算的位元節點數目來減少功率消耗，並且在特定的解碼回數中會喚醒所有的節點來更新訊息以將位元錯誤率減至最低。除此之外，我們也研究了兩種更低硬體成本的衍生演算法，針對這三種演算法我們都提出了低成本的硬體架構。而模擬結果中顯示我們的演算法相較於原本的演算法最多可以減少75%最耗電的記憶體存取。而FPGA的實作結果顯示我們只增加了0.6%的硬體成本，並且在頻率140MHz時可以達到67~292Mbps的效能。For the emergency of low power consumption demand in mobile applications, a decoding operation reduction algorithm for Low-Density Parity Check (LDPC) codes is proposed. Our operation reduction layered decoding algorithm reduces active node computation to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Besides, two variation algorithms are also explored. Low hardware overhead partially parallel LDPC decoder architecture for all three decoding operation reduction algorithms is also described. Simulation results show that our algorithm reduces the number the most power consuming memory access operation up to 75% compared to the original layered decoding. The FPGA implementation results show that our architecture only add 0.6% hardware cost and the throughput is up to 67~292Mbps at frequency 140MHz.中文摘要...................................................iBSTRACT..................................................iiONTENTS.................................................iiiIST OF FIGURE............................................viIST OF TABLE...........................................viiihapter 1 ntroduction......................................1.1 Digital Communication System Overview..................1.2 Low-Density Parity-Check Code Overview.................2.3 Motivation.............................................3.4 Power Consumption in Digital CMOS Circuits.............4.5 Thesis Organization....................................5hapter 2 Backgrounds......................................6.1 LDPC Codes.............................................6.1.1 Matrix Representation of LDPC Codes..................6.1.2 Graph Representation of LDPC Codes...................7.1.3 Quasi-Cyclic LDPC Codes..............................8.2 LDPC Decoding Algorithms...............................9.2.1 Sum-Product Algorithm...............................10.2.2 Min-Sum Algorithm...................................10.3 Decode Scheduling Scheme..............................15.3.1 Two-Phase Scheduling Scheme.........................15.3.2 Horizontal Layered Scheduling Scheme................16.3.2 Vertical Layered Scheduling Scheme..................18.4 Related Works of Low Power Consumption LDPC Decoder...21.4.1 Joint Code-Decoder Design...........................21.4.2 Threshold Decoding..................................21.4.3 Early-Termination Scheme............................22.4.4 Lazy Scheduling.....................................23.4.5 Dynamic Voltage Scaling Frequency...................23.4.6 Power Dissipation Analysis in LDPC Decoder..........24hapter 3 The Proposed Operation Reduction Layered Decoding Algorithm with Periodic Update............................25.1 Low Power LDPC Decoder Design Considerations..........25.1.1 SPA vs. MSA.........................................25.1.2 Horizontal Layered Scheduling Scheme vs. Vertical Layered Scheduling Scheme.................................26.1.3 Reduce the Computation and Memory Access of the Horizontal Layered Scheduling Scheme......................29.2 Low Hardware Complexity BER Compensation Scheme.......29.3 Scenario of the Decoding Operation Reduction Algorithm.................................................30.4 Formulation of the Decoding Operation Reduction Algorithm.................................................31.5 Variation of the Decoding Operation Reduction Algorithm.................................................33hapter 4 The Proposed Hardware Architecture..............36.1 IEEE 802.16e LDPC Code Parity-Check Matrix............36.2 The Decoder Architecture Overview.....................37.2.1 Data Path of the Decoder............................37.2.2 Control Unit........................................39.2.3 Left Rotator and Right Rotator......................39.2.4 Decode Processing Unit..............................39.3 Modification Units....................................40.4 Memory Structure......................................41.5 The Operation Reduction...............................42.6 Architecture of Variation Algorithms..................42hapter 5 Simulation and Implementation Results...........45.1 The FPGA Design Flow..................................45.1.1 System Level........................................47.1.2 RTL Level...........................................47.1.3 FPGA Level..........................................48.2 Algorithm Simulation Results..........................49.2.1 Parameter Adjustments...............................49.2.2 Operation Reduction of Variation Algorithms.........52.2.3 Performance Comparison between Algorithms...........53.3 FPGA Implementation Results...........................55hapter 6 Conclusion and Future Works.....................58.1 Conclusion............................................58.2 Future Works..........................................58EFERENCE.................................................60application/pdf2079770 bytesapplication/pdfen-US低密度奇偶校驗碼低功率解碼器LDPClow-powerdecoderthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/184876/1/ntu-97-P94922003-1.pdf