電機資訊學院: 電子工程學研究所指導教授: 李建模謝詩安Hsieh, Shih-AnShih-AnHsieh2017-03-062018-07-102017-03-062018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/276662本論文一個針對雙軌非同步電路的測試技術：DR-scan。本文提出了一個完全掃描的可測試技術，其應用了非同步的雙軌邏輯電路的個編碼，達到掃描鍊在轉移時無需時脈。本文的可測試設計技術可以被應用在許多的實作方法，如：DIMS、NCL、PCHB。本技術應用了傳統的完全掃描自動測試圖樣產生器來產生高錯誤涵蓋率的測試圖樣。實驗結果顯示16位元線性管路乘法器的額外面積僅有9%。在非線性管路電路上的錯誤涵蓋率皆高於98%。This thesis presents a test methodology, Dual-rail scan (DR-scan), for dual-rail asynchronous circuits. We propose a full-scan design for testability (DfT) technique, which uses all four codewords in dual-rail logic so that scan chains can be shifted without clock. Our DfT can be applied to various implementations, including delay insensitive minterm synthesis (DIMS), null conventional logic (NCL), and pre-charge half buffer (PCHB). DR-scan enables traditional full-scan automatic test pattern generation (ATPG) to generate high fault coverage test patterns. Experimental results show area overhead of 16-bit multiplier linear pipeline is only 9%. Fault coverage on non-linear pipeline circuits are higher than 98%.論文使用權限: 不同意授權非同步電路雙軌邏輯電路掃描鍊可測試設計測試圖樣產生Asynchronous circuitsDual-rail logicScan chainDesign for testabilityTest pattern generationthesis