2011-11-012024-05-18https://scholars.lib.ntu.edu.tw/handle/123456789/697667摘要：現今半導體以及微機電元件, 隨著市場的需求, 朝向<1>低耗電以及<2>高效 能二大方向演進, 同時元件尺寸也微縮越小已滿足莫爾定律, 在<1> 低耗電方面, 高 介電係數材料已經被廣泛的使用, 而在<2>高元件效能的提升上面, 微奈米級應變矽 技術是近來最被注重的技術, 國際大廠: 英特爾(Intel), 美商國際儀器公司(IBM), 日本富士通(FSL), 與台灣積體電路公司(TSMC)等, 均投入大量的研究經費, 用以研 究奈米級應力的最佳化. 目前被廣泛使用研究的應力來源有: 矽鍺應力, 金屬應力, 以及缺陷應力等等.. 此計畫希望探討出對於高效能半導體與微機電元件, 最佳的微應 力模式, 包含: 結構製程模擬, 應力模型的建立, 以及製程的最佳化條件邊界研究. 以期能夠達到尖端元件機械應力設計開發與教學研究的目標. 研究計畫共分三年(三 期), 預計達成的目標有<第1 年> 分析最佳奈米應力源模式以及應力模擬的模型建立. <第2 年> 利用機械材料模組實驗, 驗證大型元件對於奈米應力的響應行為, 同時進行 模擬與實驗的驗證, <第三年> 利用驗證過後的模擬模型提出奈米應力的最佳化, 同時 與台灣積體電路公司(TSMC)合作進行準確性驗證提升. 此計畫完整包含相關理論分析, 應力模擬, 與實驗驗證,進而提出完整模型. 具有提升研究能量以及提升與業界合作產 學關係的目的.<br> Abstract: In this project, we investigate that the high CMOS performance can be achieved by advanced nano-level strained Si technology. It includes ultra-high-compressive-stress-contact-etching-stop layer stressor, embedded SiGe source/drain (S/D) stressor with high Ge concentration, and optimal nano-stress design of the device dimensions. The optimum nano-stress design of the device structure results in a suitable 3D stress distribution in the channel and further has better electric performance for both n FET and pFET, in terms of Ion-Ioff enhancement, ballistic efficiency, and injection velocity. In our previous study, multi-channel devices with symmetric W and L (gate width/gate length ratio is <10) are proposed to enhance the nFET device performance in circuit designs. For pFETs, commonly used wide W inherits uniaxial-like stress, and devices with symmetric W and L (gate width/gate length ratio is < 10) should be avoided in high performance circuit designs. The characteristics of the detailed nano-stress simulation and the ballistic transport measurement reported in this work suggest that these results remain valid for ballistic transport devices with 10-20 nm gate lengths. The pFET 3D nano-stress distribution with different device dimensions was simulated by 3D finite element mechanical stress simulation, and the mobility, ballistic efficiency, and injection velocity were calculated theoretically and measured based on the stress characteristics. Moreover, the pFET channel stress characteristic from the high-compressive-stress-contact-etching-stop layer and embedded SiGe S/D stressor has also been further decoupled and investigate these effects on the advanced device performance booster.應變矽技術機械應力Strained Si TechnologyMechanical stress