Layer minimization in escape routing for staggered-pin-array PCBs

Ho, Y.-K.Y.-K.HoShih, X.-W.X.-W.ShihChang, Y.-W.Y.-W.ChangCheng, C.-K.C.-K.ChengYAO-WEN CHANG2018-09-102018-09-102013http://www.scopus.com/inward/record.url?eid=2-s2.0-84877774962&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/380154Layer minimization in escape routing for staggered-pin-array PCBsconference paper10.1109/ASPDAC.2013.65095942-s2.0-84877774962