Huang S.-JLin Y.-HWeng C.-HYI-CHANG LU2023-06-092023-06-092021https://www.scopus.com/inward/record.uri?eid=2-s2.0-85126661386&doi=10.1109%2fAPCCAS51387.2021.9687624&partnerID=40&md5=9247efc8fdabd3a3979342f1a727723ehttps://scholars.lib.ntu.edu.tw/handle/123456789/632094Video recording has become one of the key features of digital cameras nowadays. Though the resolution and quality of frames are the key specs, the stability issue is less addressed. The amount of data involved in video stabilization makes memory bandwidth a bottleneck. Hence existing hardware accelerators are usually designed using a simple approach of displacement compensation, which has limited the performance. In this work, we design a special processor capable of providing a better stabilization function in real time. The hardware techniques implemented include pipelining, parallel processing, memory interleaving, and data ordering. The chip is synthesized with TSMC 40nm technology. An 11X speedup can be achieved when compared to the software version. © 2021 IEEE.feature point; hardware architecture; Video stabilizationMemory architecture; Stabilization; Feature point; Global mesh; Hardware architecture; Key feature; Memory bandwidths; Mesh warping; Real time videos; Stability issues; Video stabilization; Video stabilizers; Video recordingconference paper10.1109/APCCAS51387.2021.96876242-s2.0-85126661386