A 2.5 GHz all-digital delay-locked loop in 0.13 mu m CMOS technology

Yang, Rong-JyiRong-JyiYangSHEN-IUAN LIU2020-06-112020-06-1120070018-9200https://scholars.lib.ntu.edu.tw/handle/123456789/499866A 2.5 GHz, 30 mW, 0.03 mm 2 , all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.[SDGs]SDG7A 2.5 GHz all-digital delay-locked loop in 0.13 mu m CMOS technologyjournal article10.1109/JSSC.2007.906183WOS:000250524500003