Gupta MVITA PI-HO HU2022-04-252022-04-252021https://www.scopus.com/inward/record.uri?eid=2-s2.0-85108151904&doi=10.1109%2fVLSI-TSA51926.2021.9440137&partnerID=40&md5=b652ae62abdb6d471dcf8206c3299090https://scholars.lib.ntu.edu.tw/handle/123456789/607350This work investigates the switching time in negative capacitance (NC) junctionless (JL) and inversion mode (IM) transistors through calibrated simulations. Results highlight that NCJL devices designed with an optimal underlap of 6 nm and appropriate gate work-function achieve a higher effective drain current than NCIM transistors. Our results show that a higher effective drain current improves the switching time in NCJL devices at a shorter gate length of 14 nm. Besides, the impact of device parameters on the switching time of NCJL and NCIM devices is analyzed. Results reported for the first time provide new viewpoints on designing logic circuits using NCJL transistors with improved switching time. ? 2021 IEEE.CapacitanceDrain currentLogic designSwitchingTransistorsVLSI circuitsDevice parametersGate lengthGate work functionInversion modesJunctionless transistorsNegative capacitanceSwitching timeComputer circuits[SDGs]SDG7conference paper10.1109/VLSI-TSA51926.2021.94401372-s2.0-85108151904