指導教授：楊佳玲臺灣大學：資訊工程學研究所林仲祥Lin, Chung-HsiangChung-HsiangLin2014-11-262018-07-052014-11-262018-07-052014http://ntur.lib.ntu.edu.tw//handle/246246/261470DRAMs are used as the main memory in most computing systems today. However, memory system performance has been historically lagged behind CPU performance, and this problem exacerbates in a multi-core system since memory resources are shared by multiple cores on a chip. To sustain concurrent memory requests from multiple cores, the speed, bandwidth, and capacity of DRAM memories continue to increase. Studies show that DRAMs now consume a significant part of the overall system power, and the temperature of DRAMs is also approaching its limit. Therefore, the challenge that we are facing today from DRAM memory management is how to achieve desired DRAM power reduction, and meet the performance and thermal constraints at the same time. Since the background power of DRAMs usually consumes more than 50% of the total DRAM power, I focus on reducing DRAM background power with negligible performance overhead, and meeting the DRAM thermal constraint in this dissertation. The background power of DRAMs is composed of power consumption of peripheral leakage which depends on DRAM power states and refresh power. To reduce the DRAM peripheral leakage, I propose a joint performance, power and thermal management framework (PPT) through orchestrating task execution and page allocation to exploit DRAM low-power modes efficiently. The PPT framework adapts to system loading to maximize peripheral leakage power savings and avoid memory thermal hotspot at the same time whiling sustaining the system bandwidth demand. For refresh power reduction, I propose SECRET (Selective Error Correction for Refresh Energy reducTion) that is designed to reduce the inevitable refresh processes by prolonging the refresh interval and correcting the retention errors by ECC (Error Correcting Code). The key observation I make is that retention errors can be treated as hard errors rather than soft errors, and only few DRAM cells have large leakage to cause retention errors. Therefore, instead of equipping error correction capability in all memory cells as existing ECC schemes, I only allocate error correction information to leaky cells under a refresh interval to minimize the overheads of ECC. The architectural supports for these two techniques do not conflict, so they can be used at the same time. Since both techniques incur negligible performance degradation, adopting them together would only hurt performance slightly as well. The effectiveness for power reduction and thermal control of these two techniques used simultaneously is as good as that of these two techniques used separately, because they reduce different parts of the DRAM background power and there is no interference between these two methods. So, utilizing the PPT and SECRET frameworks can reduce both the peripheral leakage power and refresh power of DRAM systems and alleviate the operating temperature with negligible overheads in performance and hardware modifications.中文摘要i Abstract ii List of Figures vii List of Tables ix Chapter 1. Introduction 1 Chapter 2. Related Work 5 2.1 Peripheral Leakage Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 Idle Period Prolongation . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1.1 Power-Aware Data Allocation . . . . . . . . . . . . . . . . . 6 2.1.1.2 Temporal Alignment of Memory Requests . . . . . . . . . . . 8 2.1.1.3 Data Re-computation . . . . . . . . . . . . . . . . . . . . . . 10 2.1.1.4 Thermal Drawback of Request Clustering . . . . . . . . . . . 10 2.1.2 Power Mode Decision . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Refresh Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 Refresh Reduction by Sensing Leakage Current . . . . . . . . . . . . . 14 2.2.2 Refresh Reduction by Considering Access Pattern . . . . . . . . . . . 15 2.2.3 Refresh Reduction by Considering Data Property . . . . . . . . . . . . 16 2.2.4 Multi-Period Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 ECC for Refresh Reduction . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.6 Adaptive Refresh Interval . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Dynamic Thermal Management for DRAMs . . . . . . . . . . . . . . . . . . 24 2.4 Reliable Low-Voltage Operation for SRAM Cache . . . . . . . . . . . . . . . 26 2.5 Related Work Using Ideas Similar to the PPT Framework . . . . . . . . . . . 29 Chapter 3. Introduction to DDRx-SDRAM 31 3.1 DRAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Power States of DDRx-SDRAM . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 DRAM Refresh Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chapter 4. PPT Framework: DRAM Peripheral Leakage Reduction with Thermal Control 35 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 The PPT Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 Adaptive Grouping Mechanism . . . . . . . . . . . . . . . . . . . . . 37 4.2.1.1 PPT Configuration Selection . . . . . . . . . . . . . . . . . . 38 4.2.1.1.1 Static Bandwidth (BW) Estimation Method . . . . 38 4.2.1.1.2 Dynamic Bandwidth (BW) Estimation Method . . 40 4.2.1.2 New PPT Configuration Adoption . . . . . . . . . . . . . . . 42 4.2.1.3 Architectural Support . . . . . . . . . . . . . . . . . . . . . . 44 4.2.2 Thermal Control Policy . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 Evaluation to PPT Framework . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3.2.1 Power/Performance Evaluation of Adaptive Grouping . . . . 49 4.3.2.2 Deferred Page Migration Analysis . . . . . . . . . . . . . . . 56 4.3.2.3 Power State Analysis . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.4 Thermal Evaluation . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.2.5 Summaries of Performance, Power and Temperature of PPT . 61 Chapter 5. SECRET Framework: DRAM Refresh Power Reduction 63 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 The SECRET Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2.1 Main Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2.2 Candidates of the Error Correcting Scheme in SECRET . . . . . . . . 65 5.2.2.1 Hamming Code ECC . . . . . . . . . . . . . . . . . . . . . . 65 5.2.2.2 Bose-Chaudhuri-Hocquenghem (BCH) Code ECC . . . . . . 65 5.2.2.3 Error Correcting Pointer . . . . . . . . . . . . . . . . . . . . 66 5.2.3 Selective Error Correction (SEC) . . . . . . . . . . . . . . . . . . . . 66 5.2.4 Off-line Phase: ECP Directory/ECPs Construction . . . . . . . . . . . 70 5.2.5 Refresh Interval Adaptation . . . . . . . . . . . . . . . . . . . . . . . 71 5.2.5.1 Profiling Memory Cells for Refresh Interval Adaptation . . . 72 5.2.5.2 Deduction of the Worst Case Leakage Ratio . . . . . . . . . . 73 5.2.5.3 Proof of the Correctness of Refresh Interval Adaptation . . . . 74 5.2.6 Discussion on Overheads of SEC . . . . . . . . . . . . . . . . . . . . 76 5.3 Evaluation to SECRET Framework . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.2.1 Design Space Exploration: Deciding Target Error Rate and SEC Cache Configuration . . . . . . . . . . . . . . . . . . . 80 5.3.2.2 Energy Analysis . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.2.3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . 84 5.3.2.4 Evaluating SECRET with Reduced Last-level Cache Size . . 85 5.3.2.5 Evaluation of Distributing Leaky Cells with Spatial Locality . 87 5.3.2.6 Comparison with Traditional ECC Approaches . . . . . . . . 89 Chapter 6. Conclusion 91 Bibliography 952336324 bytesapplication/pdf論文公開時間：2014/08/25論文使用權限：同意無償授權動態隨機存取記憶體功率溫度週邊電路刷新[SDGs]SDG16thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/261470/1/ntu-103-F94922040-1.pdf