Analysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulation

National Taiwan University Dept Elect EngnChen, Chien-ChungChien-ChungChenKuo, James B.James B.KuoSu, Ke-WeiKe-WeiSuLiu, SallySallyLiu2006-11-142018-07-062006-11-142018-07-062006-10http://ntur.lib.ntu.edu.tw//handle/246246/200611150121241This paper reports an analysis of the gate–source/ drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 μm, the inner-sidewall-oxide fringing capacitance (CFIS), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at VG = 0.3 V and VD = 1 V, is the second largest contributor to the gate–source capacitance (CGS). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 μm, CFIS cannot be overlooked for modeling gate–source/drain capacitance (CGS/CGD).application/pdf823010 bytesapplication/pdfzh-TWCapacitanceCMOSFETsmodelingsilicon-oninsulator (SOI) technology, simulationAnalysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulationjournal articlehttp://ntur.lib.ntu.edu.tw/bitstream/246246/200611150121241/1/169.pdf