曹恆煒臺灣大學：電信工程學研究所黃俊迪Huang, Hun-TiHun-TiHuang2007-11-272018-07-052007-11-272018-07-052004http://ntur.lib.ntu.edu.tw//handle/246246/58564I/Q 不平衡是所有I/Q調變系統中都會遭遇到的問題。在接收機前端的類比電路製程變異將會造成電路的不匹配，因此增益不平衡及相位不平衡是不可避免的，數位類比轉換器的電容不匹配也會造成此一問題。I/Q不平衡問題將會造成接收機的鏡像干擾排斥能力大幅降低，鏡像干擾將使得欲接收的信號嚴重失真。 在本篇論文中，提出了一個數位式I/Q不平衡補償技術。使用sign-sign LMS可適性濾波器理論來偵測出I/Q不平衡的參數，然後使用兩個乘法器以及一個直接數位頻率合成器(DDFS)來實現增益不平衡以及相位不平衡的補償。接收機前端的類比電路是使用安捷倫ADS模擬;而數位補償的架構則是使用Matlab Simulink模擬。模擬結果顯示此架構可幾乎完全補償I/Q不平衡，和其他補償方法的比較也顯示此架構提供較好的補償效果及較少的硬提複雜度。最後，我們使用雙通道的類比對數位轉換器(AD9238)及可編程邏輯元件(ALTERA APEX20K1500E)進行驗證，實驗結果顯示:此補償架構可提供高達63dB的鏡像干擾排斥比，合乎了WCDMA以及MCCDMA系統的要求。I/Q imbalance appears in all I/Q communication systems. Process variation in the analog front-end of the receiver will cause mismatches in the components. Gain and phase mismatches between I and Q mixers are unavoidable. The capacitor mismatches in analog-to digital converters also cause this problem. I/Q imbalance problem causes finite rejection in the image frequency band, and the image interference will alias into the desired signal, severe distortion will occur. In this work, a novel and feasible I/Q imbalance compensation technique is proposed. A sign-sign LMS algorithm is used to detect the imbalance of the analog front-end. After that, two multipliers and a DDFS (Direct Digital Frequency Synthesizer) are employed to perform high precision amplitude and phase imbalance compensation. In this work, the analog front end is simulated by Advanced Design System and the digital compensation architecture is simulated by Matlab Simulink. Simulation results show that this architecture can eliminate I/Q imbalance almost completely without disturb the desired signal. Comparisons between this algorithm and other techniques are also performed, which show that this work can provide better performance with less hardware complexity. Finally, this compensation system is implemented in an ALTERA FPGA(APEX20K1500E) and Analog Device 12-bits dual channel ADC (AD9238). Experiment results show that IRR as high as 63 dB is achieved, which provides sufficient image rejection in both 3GPPWCDMA and MCCDMA system. This algorithm makes low-IF receiver a more attractive candidate in modern receivers.Contents 1 Introduction 1 1.1 Motivation…………………………………………………1 1.2 Organization of The Thesis……………………………1 2 Receiver Architectures…………………………………3 2.1 General Considerations…………………………………3 2.1.1 Intermodulation and Circuit Linearity…………….3 2.1.2 Sensitivity and Noise Figure…………………………3 2.2 Receiver Architectures…………………………………7 2.2.1 Heterodyne Receivers……………………………………7 a Architecture………………………………………………7 b Problems of Heterodyne Receivers………………….9 2.2.2 Homodyne Receivers……………………………………10 a Architecture……………………………10 b Problems of Homodyne Receivers……10 2.2.3 Image Reject Receiver…………………13 2.2.4 Comparison………………………………20 3 OFDM System and Impacts of I/Q Imbalance…………23 3.1 OFDM Systems………………………………………………23 3.1.1 OFDM Basics………………………………………………23 3.1.2 Using IFFT to Generate Orthogonal Subcarriers…25 3.1.3 Guard Time and Cyclic Extension……………………26 3.2 Impacts of I/Q Imbalance in OFDM System…………27 3.2.1 Zero IF Receiver………………………………………27 3.2.2 Low-IF receiver…………………………………………31 4 Proposed Receiver Architecture………………………37 4.1 RF Module…………………………………………………37 4.2 IF Module…………………………………………………42 5 I/Q Imbalance Compensation in Low-IF Receivers…49 5.1 Key Idea of I/Q Imbalance Compensation……………49 5.2 Digital I/Q Imbalance Compensation Techniques…50 5.2.1 Using DDFS for I/Q Imbalance Compensation………50 5.2.2 Blind Image Interference Cancellation……………73 5.3 Comparison…………………………………………………78 6 Experiment Results……………………………………81 6.1 Experiment Result of DDFS phase tuning……………81 6.2 Experiment Result of Sign-Sign LMS Calibration…86 6.3 Experiment Result of ADC and FPGA…………………88 7 Conclusion………………………………………………95 Appendix A Photos of Experiment Equipments………………979555359 bytesapplication/pdfen-USI/Q不平衡低中頻式接收機直接數位頻率合成器direct digital frequemcy synthesizerI/Q imbalanceLow-IF receiverthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58564/1/ntu-93-R91942095-1.pdf