臺灣大學: 電信工程學研究所莊晴光柯佩均Ko, Pei-ChunPei-ChunKo2013-03-272018-07-052013-03-272018-07-052010http://ntur.lib.ntu.edu.tw//handle/246246/253364　　本論文主要分成兩大部份，第一部分是利用0.18微米互補性金屬氧化物半導體(CMOS)製程，提出一個24 GHz極小型之低功耗低雜訊放大器;另一部份是利用0.13微米互補性金屬氧化物半導體(CMOS)製程，提出一個24 GHz可調式延遲線以及兩種損耗補償延遲線之設計。以上兩種元件皆在K頻段之調頻連續波(FMCW)雷達系統中佔有重要地位。此外，為了能夠有效縮小面積以利於單晶系統整合，本論文利用所提出的互補式金屬傳輸線(CCS TL)來設計在射頻電路上佔去絕大部分面積的被動元件，此互補式金屬傳輸線的可曲折特性繞線佈局，不僅可以達到電路微小化，還可以利用格子狀結構的參考接地來維持整個電路在矽基板上的好的隔離度。 　　首先，本論文提出一24 GHz極小型之低功耗低雜訊放大器，巧妙的使用兩個以CCS TL為基礎設計的變壓器(transformer)分別達到(1)輸入阻抗和雜訊阻抗的最佳匹配以及(2)中間級共軛匹配，同時利用gain peaking 技術來提高整體增益。佈局完成後之整體面積為0.26 mm 0.29 mm，量測結果顯示使用1.8 V的偏壓時，消耗電流為3 mA，增益可達到9.2 dB，的確同時達到極小型、低功耗及高增益之設計，然而量測到的雜訊指數為12 dB，與模擬有所誤差。 　　接下來，本論文又提出了一操作在24 GHz之可調式延遲線，利用改變反射類型(reflection type)電路的負載組合型態，成功的將原本適合操作在低頻的延遲線提升到方便於高頻操作，在24 GHz時，時間延遲可達到128 psec，然而，此種架構卻出現了無可避免的入射損耗變化(IL variation)，因此，另外提出兩種損耗補償方式，一種為被動元件補償，另一種為主動元件補償。被動元件補償及主動元件補償分別是利用在負載端多並聯一電阻，以及在負載端多串聯一負電阻以減輕因負載端元件本身的不理想效應對整體電路所產生的影響。模擬結果顯示，在維持幾乎相同的時間延遲情況之下，提出的兩種補償方式皆可降低入射損耗變化範圍，尤以主動補償方式效果更為明顯，可從原本的7.5 dB降為接近0 dB。　　There are two parts in this thesis, one is a 24 GHz low-power consumption low-noise amplifier with miniaturized size in 0.18 μm CMOS process, and the other is a 24 GHz monolithic variable delay line and two delay lines with loss compensation in 0.13 μm CMOS process. These two components are very important in K-band FMCW radar system. To reduce the chip size for systematic integration, the CCS transmission line was adopted to design the passive elements that are bulky in RF circuits. The CCS transmission line is useful for minimization of the chip size because it is flexible and meanderable during layout procedure. Moreover, the mesh ground plane also provides a good isolation between the circuit and the Si substrate. 　　First, this thesis proposes a 24 GHz low-power consumption low-noise amplifier with miniaturized size. Two CCS TL based transformers were used in the amplifier to reach (1) the optimal matching for input and noise impedances and (2) conjugate matching for medium stage. Moreover, the gain peaking technique was also adopted to improve the entire performance. The total size of the proposed amplifier was 0.26 mm×0.29 mm. The measured results show the gain of the amplifier was 9.2 dB with 1.8 V bias voltage and 3 mA DC current. It proves that the design is very compact and has low power consumption with higher gain. However, the noise figure was 12 dB that is different from the simulation. 　　The other proposed component is a 24 GHz monolithic variable delay line. The monolithic variable delay line is often operated in lower frequency. This thesis raises the operation frequency of the variable delay line from low to high by changing the load combination of the reflection type circuit. The time delay reached to 128 psec when the operation frequency was 24 GHz. However, the proposed structure results in the unavoidable insertion loss variation. Therefore, two loss compensation methods are proposed, the passive compensation and active compensation. To overcome the large insertion loss variation attributed to the non-ideal components, the passive compensation method had the identical resistors in parallel with the loads and the active compensation method had the negative impedances in series with the loads. The simulation results show that these methods both reduce the insertion loss variation under the nearly time delay, especially in the active compensation which could reduce the insertion loss variation from 7.5 dB to 0 dB.6082481 bytesapplication/pdfen-US24 GHz極小型之低功耗低雜訊放大器互補式金屬傳輸線變壓器可調式延遲線被動元件補償主動元件補償miniaturized low-power low-noise amplifier (LNA)complementary-conducting-strip transmission line (CCS TL)transformervariable delay linepassive compensationactive compensationhttp://ntur.lib.ntu.edu.tw/bitstream/246246/253364/1/ntu-99-R97942014-1.pdf