Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

Chiang, K.-Y.K.-Y.ChiangHo, Y.-H.Y.-H.HoChen, Y.-W.Y.-W.ChenPan, C.-S.C.-S.PanCHIEN-MO LI2020-06-292020-06-292015https://scholars.lib.ntu.edu.tw/handle/123456789/505966Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuitsconference paper10.1109/ATS.2015.382-s2.0-84963622288https://www.scopus.com/inward/record.uri?eid=2-s2.0-84963622288&doi=10.1109%2fATS.2015.38&partnerID=40&md5=095ade071726bed33ff8792a58c5327d