陳中平臺灣大學：電子工程學研究所郭明璋Kuo, Ming-ZhangMing-ZhangKuo2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57539這篇論文的主題是描述如何實現一個四千位元的靜態隨機存取記憶體電路。為了要達到可以在低工作電壓下正確地讀取資料，本文提出了一種改良式電流栓鎖感測放大器電路。這篇論文總共分為五個章節，其中第一章及第五章為導論及結論，在第二章裡，將會介紹整體靜態隨機存取記憶體的電路架構，同時也將介紹各個基本電路及其設計考量。 在第三章裡我們將分析感測放大器。 由於輸入阻抗的差異，感測放大器在時間延遲的表現上有很大的差別。同時也將介紹幾種常用的感測放大器並分析其優缺點以及對常用的電流栓鎖感測放大器作些微的修改使其適用於低工作電壓。 第四章裡詳述了電路實作，我們使用0.18um標準互補式金氧半製程實現一個四千位元的靜態隨機存取記憶體電路。我們所實現的靜態隨機存取記憶體電路讀取延遲時間為2.0557nS。晶片的主體佔了1.056002 ╳ 1.090342 mm2，當電路工作在250MHz的情況下，整個電路消耗了15.658毫瓦。Abstract This thesis describes the implementation of a 4Kb static random access memory circuit. In order to correctly perform a read operation at low voltage, the current latched sense amplifier is improved. This thesis is divided into five chapters. The first chapter is the introduction. In the chapter 2, the architecture and the design considerations of SRAM are presented. In chapter 3, we describe the sense amplifiers in detail. The difference of the input resistance makes the delay differ a lot in sensing time. Chapter 4 presents the circuit implementation. A 4Kb SRAM is implemented with a standard 0.18um CMOS process. The access time of SRAM is 2.0557ns. The core circuit of the chip occupies 1.056002 ╳ 1.090342 mm2 and it consumes 15.658mW when working at 250MHz.1. Introduction 1 1-1 Motivation……………………… 1 1-2 Organization…………………… 2 2. SRAM Architecture 3 2-1 Memory organization………… 3 2-2 Operation modes…………………5 2-2-1 Read operation……………… 5 2-2-2 Write operation…..…………7 2-3 Timing and power analysis……8 2-3-1 Memory timing parameters… 8 2-3-2 Power analysis in the simple SRAM…..….... 10 2-3-3 Delay analysis in the simple SRAM… ………. 11 2-4 Divided word line………………….……… …….. 13 2-4-1 Power consumption in the divided word line structure 14 2-4-2 Delay in the divided word line structure…..……….... 15 2-5 Memory circuits…………………….………………………..... 16 2-5-1 SRAM Cells……………………………...................... 16 2-5-2 Decoders…..………..................................................... 18 2-5-3 Column precharge circuits…........................................ 23 2-5-4 Sense amplifier............................................................. 25 2-5-5 Replica circuit............................................................... 25 2-6 Summary................................................................................. 28 3. Sense amplifier 29 3-1 Sense amplifier classification………………………………... 29 3-2 Delay analysis in voltage and current sense amplifiers……… 30 3-3 Conventional CMOS differential amplifier.............................. 32 3-4 Latch type sense amplifier………………………………........ 36 3-5 Current latched sense amplifier................................................ 38 3-6 The improved current latched sense amplifier......................... 40 3-7 Summary................................................................................... 43 4. A 4Kb SRAM circuit design 45 4-1 Introduction………………………………………….............. 45 4-2 Cell array…………….............................................................. 46 4-2-1 Divided Word Line…………………………….......... 46 4-2-2 Cell stability…..………............................................... 47 4-2-3 Layout…...................................................................... 48 4-3 Decoder………......................................................................... 49 4-4 Sense amplifier…………………………………………......... 51 4-5 4Kb SRAM simulation result................................................... 56 4-6 Conclusions.............................................................................. 59 5. Conclusions 61 6. References 632729770 bytesapplication/pdfen-US記憶體SRAMthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57539/1/ntu-94-R92943065-1.pdf