A transistor sizing method for standard-cell optimization considering lithography effects

Jia-Syun CaiPin-Yuan SuChien-Lin LeeKuen-Yu TsaiNeal V. LaffertyHarsha Grunes2024-08-122024-08-122024-04-10https://scholars.lib.ntu.edu.tw/handle/123456789/720191A transistor sizing method for standard-cell optimization considering lithography effectsconference paper10.1117/12.3012028