呂學士臺灣大學:電子工程學研究所潘建文Pan, Chien-WenChien-WenPan2010-07-142018-07-102010-07-142018-07-102009U0001-1408200913161200http://ntur.lib.ntu.edu.tw//handle/246246/189149近年來隨著通訊科技的進步，人們的生活獲得很大的便利。其中正交分頻多工系統(OFDM)被廣泛的應用在有線及無線的區域網路，例如: ADSL, Wimax, 3G, 4G等。原因在於OFDM系統主要的優點不僅有效對抗載波間干擾(Inter-Carrier Interference)與符元間干擾(Inter-Symbol Interference)，並能增加頻帶的利用率。其中快速傅立葉轉換處理器(FFT)為OFDM的系統核心。因此，在本論文中我們設計與實現一個正逆快速傅立葉轉換處理器(FFT/IFFT)。應不同的應用層面所需的OFDM系統規格也不同，所以使用不同的FFT點數。晶片的面積與硬體的需求會隨著所使用的FFT點數增加而增加。由於本論文為我們實驗室第一個DSP晶片，所以使用FFT 64 points來設計與實現。們採用radix-2/4/8演算法和pipeline-based SDF架構來減少算數複雜度與硬體需求。在本論文中FFT/IFFT處理器使用台積電0.35μm 2P4M CMOS製程完成晶片製作，接著進行量測，實驗結果與模擬相同。The life attains much convenience with the advanced communication technology in recent years, among which the system named Orthogonal Frequency Division Multiplexing (OFDM) is extensively put in use in wired and wireless local area network such as ADSL, Wimax, 3G, 4G and so on. The fact is resulted not only from the advantages in OFDM systems which can effectively reduce inter-carrier interference (ICI) and inter-symbol interference (ISI) caused by multipath effect, but also from improving the utilization of channel, and the FFT/IFFT is a core of OFDM technique. Therefore, we designed and implemented a FFT/IFFT processor in this thesis. According to the different perspectives of the applications needing the specific OFDM systems, they use different FFT points. The requirements of the area and hardware in chip will increase caused by FFT size. Because of this thesis is the first one of DSP chips in our Lab, we use FFT 64 points to design and implement. We adopted radix-2/4/8 algorithm and pipeline-based SDF architecture to reduce the complexity of computation and the requirements of hardware. The FFT/IFFT processor was implemented by TSMC 0.35μm 2P4M CMOS process in this thesis, and through the measurements we got the same results between simulations and measurements.List of Contents Index of Figures Vndex of Tables IXhapter 1 Introduction -----------------------------------1.0 Motivation -------------------------------------------1.1 Basic Concepts of OFDM -------------------------------1.2 Thesis Organization ----------------------------------6hapter 2 FFT Algorithms ---------------------------------7.0 Introduction -----------------------------------------7.1 Decimation-in-Time Algorithm -------------------------8.2 Decimation-in-Frequency Algorithms -------------------12.2.0 Overview--------------------------------------------12.2.1 Fixed-Radix FFT Algorithms--------------------------12.2.1.1 Radix-2 DIF Algorithm---------------------------13.2.1.2 Radix-4 DIF Algorithm---------------------------17.2.1.3 Radix-8 DIF Algorithm---------------------------19.2.2 Split-Radix FFT Algorithms------------------------22.2.2.1 Radix-2/4 DIF FFT Algorithm---------------------22.2.2.2 Radix-2/8 DIF FFT Algorithm---------------------25.3 Comparison------------------------------------------28hapter 3 FFT Architectures-------------------------------30.0 Introduction------------------------------------30.1 Pipeline Architectures--------------------------31.1.0 Overview-------------------------------------------31.1.1 Single-Path Delay Feedback Architecture------------33.1.1.1 Fixed-Radix DIF SDF Architecture-----------------34.1.1.1.1 Radix-2 SDF Architecture-----------------------34.1.1.1.2 Radix-4 SDF Architecture-----------------------35.1.1.2 Split-Radix DIF SDF Architecture-----------------37.1.2 Multi-Path Delay Commutator Architecture-----------37.1.2.1 Fixed-Radix DIF MDC Architecture-----------------38.1.2.1.1 Radix-2 MDC Architecture-----------------------38.1.2.1.2 Radix-4 MDC Architecture-----------------------39.1.2.2 Split-Radix DIF MDC Architecture-----------------40.2 Comparison -------------------------------------41hapter 4 Circuit Design----------------------------------44.0 Introduction------------------------------------44.1 Proposed FFT/IFFT Processor Design--------------45.1.1 Design Flow---------------------------------------45.1.2 Proposed Algorithm--------------------------------47.1.2.1 Complex Multiplication by ---------------------47.1.2.2 Radix-2/4/8 Algorithm---------------------------49.1.3 Proposed Architecture-----------------------------51.2 Hardware Implementation-------------------------53.2.1 Butterfly-----------------------------------------53.2.1.1 Radix-2/4/8 Processing Element------------------53.2.1.2 Control Unit------------------------------------55.2.2 Multiplier----------------------------------------57.2.2.1 Constant Multiplier-----------------------------57.2.2.2 Complex Multiplier------------------------------58.2.3 Twiddle Factor Genertaor--------------------------60.2.4 FFT/IFFT Transform--------------------------------61.3 Measurement for FFT/IFFT Processor--------------62.3.1 Measurement Flow----------------------------------62.3.2 Simulation----------------------------------------63.3.2.1 Software Simulation-----------------------------63.3.2.2 Hardware Simulation-----------------------------65.3.3 FPGA Measurement Setup and Result-----------------67.3.3.1 Measurement Setup-------------------------------67.3.3.2 Measurement Result------------------------------68.3.4 Chip Measurement Setup and Result-----------------70.3.4.1 Chip Overview-----------------------------------70.3.4.2 PCB Design--------------------------------------71.3.4.3 Measurement Setup-------------------------------73.3.4.4 Measurement Result------------------------------74.4 Specification Summary and Comparison----------------76hapter 5 Conclusion and Future Work----------------------78ppendix Patent Search ---------------------------------80ibliography---------------------------------------------831297802 bytesapplication/pdfen-USOFDMFFTpipelineradix-2/4/8thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189149/1/ntu-98-J96921024-1.pdf