A 50-Gb/s 10-mW analog equalizer using transformer feedback technique in 65-nm CMOS technology

Lu, Jian-HaoJian-HaoLuSHEN-IUAN LIU2011-10-072018-07-102011-10-072018-07-10200915497747http://scholars.lib.ntu.edu.tw/handle/123456789/352073http://ntur.lib.ntu.edu.tw/bitstream/246246/237193/-1/07.pdfA 50-Gb/s low-power analog equalizer has been realized in 65-nm CMOS technology. This equalizer adopts the proposed transformer feedback technique to achieve a peaking gain of 18 dB at 25 GHz and low-power dissipation. The whole equalizer without the output buffer consumes 10 mW from a 1-V supply. The chip occupies 0.35 × 0.27 mm2. For a 50-Gb/s pseudorandom bit sequence of 27 - 1, the measured bit error rate is less than 10-12, and the measured maximum root-mean-square and peak-to-peak jitters are 2.7 and 12.4 ps, respectively. © 2009 IEEE.CMOS; Equalizer; Transformer feedbackBit error rate; CMOS integrated circuits; Feedback; Analog equalizers; CMOS technology; Low-power dissipation; Output Buffer; Peak-to-peak; Pseudo random bit sequences; Root Mean Square; Transformer feedback; EqualizersA 50-Gb/s 10-mW analog equalizer using transformer feedback technique in 65-nm CMOS technologyjournal article10.1109/TCSII.2009.2030536http://ntur.lib.ntu.edu.tw/bitstream/246246/237193/-1/07.pdf