Dept. of Electr. Eng., National Taiwan Univ.Jehng, Yeu-ShenYeu-ShenJehngLIANG-GEE CHENTZI-DAR CHIUEHChen, Thou-HoThou-HoChen2007-04-192018-07-062007-04-192018-07-061992-0502714310http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032311https://www.scopus.com/inward/record.uri?eid=2-s2.0-84941606622&doi=10.1109%2fISCAS.1992.230355&partnerID=40&md5=fcbc5320d66783aae3fe574441d63a23In this paper, a practical design technique is presented to realize the array architecture for hierarchical block matching algorithms. A mapping procedure has been applied to derive the array processor from the algorithm. The proposed systolic array is derived to reduce the I/O bandwidth and the hardware cost. This systolic array is configurated to be single-chip or cascaded architectures to match the real-time video applications. © 2012 IEEE.application/pdf373586 bytesapplication/pdfen-USImage compression; Array architecture; Block matching algorithms; Design technique; Hardware cost; Real time videos; Single chips; Video compression algorithms; Systolic arraysconference paper10.1109/ISCAS.1992.2303552-s2.0-84941606622http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032311/1/00230355.pdf