曹恆偉臺灣大學：電子工程學研究所陳治雄Chen, Chiu-ShiungChiu-ShiungChen2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57280中華民國九十五年七月 本文摘要 本論文主要探討其超取樣技術被廣泛的使用在數位音響系統之高階單一位元三角積分調變器設計.由於三角積分調變器對類比電路的非理想特性並不敏感,其中包括元件間的不匹配、運算放大器的增益等等,而這些特性對於類比電路來說尤其重要,因此三角積分調變器非常適合實現需要高解析度,高準確度,及窄寬頻的類比數位轉換器.而評估此調變器之標準包含:一、訊號雜訊比(SNR)；二、動態輸入範圍(DR) . 整篇論文描述了在為了獲得理想的訊號雜訊比與較小的電量消耗,在運算操作放大器的放大倍率、頻寬、與迴轉率上求得其對積分三角調變器之共同影響,另外運算放大器之輸出級改為Class-AB之架構以減少電量的損失.最後在交換電路的採樣開關處加入半電路模仿元件來抑止通道電荷注入所造成的誤差.藉由實驗結果顯示,在取樣頻率為6.4MHz,信號頻寬為25KHz時,亦即取樣頻率為128時,實做的三角積分調變器可達到88dB的訊號雜訊比.其對晶片的設計是使用台積電互補式金氧半0.35微米的製成,透過CIC的管道而實現.Abstract The main discussion of this thesis is to design and implement the high-order one-bit delta-sigma modulator with oversampling technique applying for stereo audio system. Due to the delta-sigma modulators are insensitive to the imperfections on the analogy components such as the device mismatch and amplifier gain. And those play important parts in the analog design. Depending on the above, we can find that the delta-sigma modulators are well suitable for realization of high-resolution, accuracy and narrow band analog-to-digital (A/D) converter. The standard estimate of this modulator include: 1. Signal to noise Ratio(SNR) 2.Dynamic Range(DR) This thesis describes that in order to achieve higher signal-to-noise ratio and lower power consumption, the SIMULINK is used to extract each influence among amplifier gain, Bandwidth and Slew Rate of the amplifier. Also, not alike before, class-AB topology are selected to be the output stage of the amplifier in order to reduce power consumption. At last, we compensate the injected charge by adding half-size dummy switches. The circuit simulation result achieves a peak signal-to-noise ratio of 88dB at a clock rate of 6.4MHz for a 25kHz signal bandwidth(OSR=128).This chip has been fabricated in a standard 0.35μm CMOS technology through CIC.Table of Contents Abstract…………………………………………………………...... Table of Content……………………………………........ 1. Introduction……………………………………………..1 1.1 Organization……………………………………………….2 2. Fundamental Principles of Delta-Sigma Modulators.3 2.1 Introduction…………………………………………..............3 2.2 Quantization Noise.............................3 2.3 Oversampling Techniques..……………………………...8 2.4 Noise-shape Delta-Sigma Modulator………........12 2.5 First-Order Delta-Sigma Modulator………………….14 2.6 Second-Order Delta-Sigma Modulator……………………16 2.7 High-Order Delta-Sigma Modulator………………………17 2.7.1Single-loop High-order Delta-Sigma Modulators.......19 2.7.2Multi-Stage Noise shaping Delta-Sigma Modulators....22 2.8 Performance Metrics………………………………………….23 2.9 Summary………………………………………………………...24 3.Design of Third-Order Single-Bit Delta-Sigma Modulators25 3.1 Introduction……………...…...................25 3.2 System level design…………….…………………25 3.2.1 Third-Order One-bit Delta-Sigma Modulator……26 3.2.2 Stability Analysis of Third-Order Delta-Sigma Modulator…30 3.2.3 The Influence of Non-idealities of Operation Amplifier on Delta-Sigma Modulator…………..32 3.3 Summary………………..38 4. Implementation of Third-Order Single-Bit Delta-Sigma Modulators...39 4.1 Introduction……………........39 4.2 Circuit Level Design…………………39 4.2.1 Switched-Capacitor Circuit………….39 4.2.2 The Operation Amplifier…………..41 4.2.3 D/A Converter………………………………………………..50 4.2.4 Regenerative Latched Comparator……..51 4.2.5 Clock Generator……………………………………………..52 4.2.6 Circuit Simulation Result………………………...54 4.3 Chip Implementation……………………………55 5. Conclusion & Future work………….....58 5.1 Conclusion……………........58 5.2 Future work……………………59 REFERENCE……………………………..61en-US三角積分delta sigmathesis