賴飛羆臺灣大學：資訊工程學研究所張紹鋒Chang, Shao-FengShao-FengChang2007-11-262018-07-052007-11-262018-07-052004http://ntur.lib.ntu.edu.tw//handle/246246/53711在本論文中，我們研究並修改一個交換器控制晶片的弁遄C快速且可實作為硬體的設計是令我們感興趣的地方，所以我們追求的目的便是要加速這個交換機控制晶片。藉由爭鋒科技公司提供一個商業化的交換機控制晶片，我們研究的主體著重於對該產品的設計與實作。這個交換機控制器必須額外配置SRAM記憶體儲存轉送表以及SDRAM記憶體當作封包緩衝區，但它的記憶體系統卻在晶片之外。在高度資料群聚性的情況下，該交換機控制器將耗費釵h時間來存取相同的記憶體資料。所以隨著傳輸頻寬與通訊埠數量的增加，這樣的情況將成為嚴重的瓶頸。我們實作了兩項弁遄G轉換表讀寫弁遄A快取表弁遄C為了驗證查表和更新的流程，我們新創了一個名為 “FTAB-RW” 的模組正確地執行讀與寫轉送表的內容。為了改善查表時間，我們使用了快取表以節省某些記憶體的存取。這樣的結果相當不錯，我們一舉省下了 9 個運作週期，將查表時間縮短為 4 到 21 個運作週期。而我們也將快取遺漏時的最差狀況維持像原始設計的狀況一樣的查表時間。不僅如此，我們更沒有額外增加任何更新流程的消耗時間。In this thesis, we investigate and modify some functions within a switch controller chip. We are interested in a fast, hardware-practicable design. And our object is to speed up the switch controller chip. In our research, we focus on a commercial product, which is a switch controller chip from EZHi-Technologies, to design and to implement. The switch controller must allocate additional SRAM memory to store forwarding table and SDRAM memory as packet data buffer, but its memory system is collocated in the way of off-chip. In the situation of high data locality, the switch controller wastes much time to access the same memory data. So it becomes a fatal bottleneck with raising transmission bandwidth and port number. We implement two functions: forwarding table R/W, cache table. In order to verify lookup and update flows, we create a module named “FTAB-RW”. It exactly executes reading and writing forwarding table. For improving lookup time, we use cache table to skip some memory access. We get a good result that save 9 clocks and improve lookup time ranging from 4 to 21 clocks. And we have the worst case is as good as original design when cache missing. Besides, we do not increase update flow time overhead.Abstract ……………………………………………………………………………….i Contents ……………………………………………………………………………....ii List of Figures ………………………………………………………………………..iv List of Tables ………………………………………………………………………....vi Chapter 1 INTRODUCTION ……………………………………………1 1.1 Foreword ……………………………………………………………………….1 1.2 Background and motivation ……………………………………………………2 1.3 Thesis organization ……………………………………………………………..4 Chapter 2 THE PRINCIPLE AND OPERATING METHOD OF SWITCH CONTROLLER ………………………………………………6 2.1 Principle of switches …………………………………………………………...6 2.1.1 Learning …………………………………………………………………...8 2.1.2 Lookup …………………………………………………………………….8 2.1.3 Forwarding ………………………………………………………………...9 2.1.4 Filtering/ Blocking ………………………………………………………...9 2.1.5 Aging/ Deleting …………………………………………………………..11 2.2 Procedures of the switch controller …………………………………………...11 2.2.1 Schedule of packet flow ………………………………………………….12 2.2.2 Forwarding table configuration …………………………………………..14 2.2.3 Input verification …………………………………………………………17 2.2.4 Output verification ……………………………………………………….21 2.3 Bottlenecks of the switch controller …………………………………………..23 iii Chapter 3 COMBINATIONS OF THE SWITCH CONTROLLER AND CACHE TABLE ………………………………………………………..25 3.1 The purpose of cache ………………………………………………………….25 3.2 Lookup and update operations of the switch controller ………………………26 3.2.1 Lookup operations of the switch controller ………………………………28 3.2.2 Update operations of the switch controller ……………………………….30 3.3 Combine cache into the switch controller …………………………………….33 Chapter 4 EXPERIMENT RESULT and ANALYSIS ………………….38 4.1 Experiment assumption and simulation ………………………………………38 4.2 Design and Implementation …………………………………………………..40 4.2.1 Forwarding table R/W function …………………………………………..40 4.2.2 Cache table function ……………………………………………………...43 4.3 Performance evaluation and analysis …………………………………………45 Chapter 5 CONCLUSIONS and FUTURE WORKS …………………..52 5.1 Conclusions …………………………………………………………………...52 5.2 Future works …………………………………………………………………..52 References ……………………………………………………………...54en-US更新查表交換機控制器轉送表快捷存取updatelookupswitch controllerforwarding tablthesis