BIST design optimization for large-scale embedded memory cores

Chien, T.-F.T.-F.ChienChao, W.-C.W.-C.ChaoLi, C.-M.C.-M.LiChang, Y.-W.Y.-W.ChangLiao, K.-Y.K.-Y.LiaoChang, M.-T.M.-T.ChangTsai, M.-H.M.-H.TsaiTseng, C.-M.C.-M.TsengYAO-WEN CHANG2018-09-102018-09-102009http://www.scopus.com/inward/record.url?eid=2-s2.0-76349089527&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/350364BIST design optimization for large-scale embedded memory coresconference paper2-s2.0-76349089527