A fully parallel ldpc decoder architecture using probabilistic min-sum algorithm for high-throughput applications

CHIA-HSIANG YANGCheng, C.-C.C.-C.ChengYang, J.-D.J.-D.YangLee, H.-C.H.-C.LeeYang, C.-H.C.-H.YangUeng, Y.-L.Y.-L.UengCHIA-HSIANG YANG2018-09-102018-09-102014http://www.scopus.com/inward/record.url?eid=2-s2.0-84906951064&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/387274[SDGs]SDG7A fully parallel ldpc decoder architecture using probabilistic min-sum algorithm for high-throughput applicationsjournal article10.1109/TCSI.2014.2312479